UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
2,418 Views
Registered: ‎10-19-2012

DCM

I AM USING SPARTAN 3E STARTER KIT. PLEASE HELP ME TO GENERATE 200MHZ CLOCK SIGNAL IN SCHEMATIC EDITOR IN XILINX.

Tags (1)
0 Kudos
1 Reply
Visitor jensmadsen
Visitor
2,393 Views
Registered: ‎10-03-2012

Re: DCM

A solution, could be something like this:

library ieee;
use ieee.std_logic_1164.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity CLK200 is
  Port ( CLK_50MHZ   : in std_logic;
         CLK_200MHz  : out std_logic;
         RESET_IN    : in std_logic;
         RESET_OUT   : out std_logic);
end CLK200;

architecture BEHAVIORAL of CLK200 is
  signal DCM_CLK_IN: std_logic;
  signal DCM_CLK_100M: std_logic;
  signal DCM_CLK_200M: std_logic;
  signal RESET: std_logic;
  signal RESET_INV: std_logic;
  signal DCM_LOCKED_OUT: std_logic;
begin
  U1: BUFG port map(I=>CLK_50MHZ, O=>DCM_CLK_IN);       -- connect to DCM_CLK_IN to 50 MHz clock

  U2: BUFG port map(I=>DCM_CLK_200M, O=>CLK_200MHZ);    -- connect DCM output to 200 MHz clock out

  U3: DCM_SP    -- Use DCM to multiply 50MHz clock to 200MHz clock
    generic map (
      CLKIN_PERIOD => 20.000, CLKIN_DIVIDE_BY_2 => FALSE, CLK_FEEDBACK => "2X",
      CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4,
      DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
      DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => X"C080",
      STARTUP_WAIT => FALSE)
    port map (
      CLKIN => DCM_CLK_IN, CLKFB => DCM_CLK_100M,
      CLK0 => open, CLK180 => open,
      CLK270 => open, CLK90 => open,
      CLK2X => DCM_CLK_100M, CLK2X180 => open,
      CLKFX => DCM_CLK_200M, CLKFX180 => open,
      LOCKED => DCM_LOCKED_OUT, STATUS => open, RST => RESET);

  U4: INV port map (I=>RESET, O=>RESET_INV);                            -- Generate inv reset
  U5: NAND2 port map (I0=>DCM_LOCKED_OUT, I1=>RESET_INV, O=>RESET_OUT); -- Generate reset out

end BEHAVIORAL;

 

 

0 Kudos