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Visitor
Visitor
6,908 Views
Registered: ‎11-10-2011

DDR2 Controller -use of DQS for reading data

Hello everyone,
I am designing DDR2 controller from scratch, right now I am trying to use DQS for reading data from memory.
I am using atalys board with spartan 6.
What I am doing is connecting the DQS in to IODELAY2 and from IODELAY2 I connecting to BUFIO2 and from there I go to ISERDES2.
I added my code for all of that path down below.
When I implement the design its fails at "Place & Route"
Is this the right way to use and connect the DQS ?????
Please help...

 

code:

 

// DQS IN FROM IOB

IOBUF gen_iob_udqsp_inst (.IO(mcbx_dram_udqs_p),.I(udqsp_wr),.T(t_udqsp),.O(udqs_p_rd));

 

//  DQS DELAYING
IODELAY2 #(
.COUNTER_WRAPAROUND("WRAPAROUND"), 
.DATA_RATE("SDR"),
.DELAY_SRC("IDATAIN"), 
.IDELAY2_VALUE(0), 
.IDELAY_MODE("NORMAL"),
.IDELAY_TYPE("FIXED"), 
.IDELAY_VALUE(63), 
.ODELAY_VALUE(0), 
.SERDES_MODE("NONE"),
.SIM_TAPDELAY_VALUE(40)
)
IODELAY2_udqsp_inst (
.BUSY(),
.DATAOUT(udqs_p_rd_delayed),  
.DATAOUT2(),                                   
.DOUT(), 
.TOUT(), 
.CAL(), 
.CE(),
.CLK(clk_0),
.IDATAIN(udqs_p_rd),
.INC(), 
.IOCLK0(),
.IOCLK1(),
.ODATAIN(),
.RST(1'b0), 
.T(1'b1)
);

 

// DQS DELAYED TO BUFIO

BUFIO2 #(
.DIVIDE(1), 
.DIVIDE_BYPASS("TRUE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("FALSE")
)
BUFIO2_inst_0 (
.DIVCLK(),
.IOCLK(clk_bufio_ioclk),
.SERDESSTROBE(strobe_bufio),
.I(udqs_p_rd_delayed) 

);

 

// DELAYED DQS TO ISERDES

genvar dq_ioi_in;
generate
for(dq_ioi_in = 0; dq_ioi_in < 16; dq_ioi_in = dq_ioi_in + 1) begin : gen_dq_in_iserdes2


ISERDES2 #(
.BITSLIP_ENABLE ("FALSE"),
.DATA_RATE ("SDR"),
.DATA_WIDTH (4), 
.INTERFACE_TYPE ("NETWORKING"), 
.SERDES_MODE ("NONE") 
)
ioi_dq_in_0
(
.CFB0(), 
.CFB1(),
.DFB(), 
.FABRICOUT(), 
.INCDEC(), 
.Q1(dq_90_rd_1[dq_ioi_in]),
.Q2(dq_90_rd_2[dq_ioi_in]),
.Q3(dq_90_rd_3[dq_ioi_in]),
.Q4(dq_90_rd_4[dq_ioi_in]),
.SHIFTOUT(),
.VALID(), 
.BITSLIP(),
.CE0(t_rd), 
.CLK0(clk_bufio_ioclk), 
.CLK1(1'b0), 
.CLKDIV(),
.D(ioi_dq_in_delayed[dq_ioi_in]), 
.IOCE(strobe_bufio),
.RST(serdes_rst),
.SHIFTIN() 
);
end
endgenerate

 

// DQ DELAYING

genvar dq_iodelay;
generate
for(dq_iodelay = 0; dq_iodelay < 16; dq_iodelay = dq_iodelay + 1) begin : gen_dq_iodelay

IODELAY2 #(
.COUNTER_WRAPAROUND ("WRAPAROUND"),
.DATA_RATE ("SDR"),
.DELAY_SRC ("IDATAIN"), 
.IDELAY2_VALUE(0), 
.IDELAY_MODE("NORMAL"), 
.IDELAY_TYPE("FIXED"), 
.IDELAY_VALUE(20), 
.ODELAY_VALUE(0), 
.SERDES_MODE("NONE"),
.SIM_TAPDELAY_VALUE(30)
)
IODELAY2_dq_in_inst
(
.BUSY(),
.DATAOUT(ioi_dq_in_delayed[dq_iodelay]), 
.DATAOUT2(), 
.DOUT(), 
.TOUT(), 
.CAL(1'b0), 
.CE(1'b0),
.CLK(clk_0),
.IDATAIN(ioi_dq_in[dq_iodelay]),
.INC(1'b0), 
.IOCLK0(clk_4x_90),
.IOCLK1(1'b0),
.ODATAIN(1'b0), 
.RST(1'b0), 
.T(1'b1)
);
end
endgenerate

 

//DQ IOB
genvar dq_i;
generate
for(dq_i = 0; dq_i < 16; dq_i = dq_i + 1) begin : gen_dq_iobuft
IOBUF gen_iob_dq_inst (.IO(mcbx_dram_dq[dq_i]),.I(ioi_dq_out[dq_i]),.T(t_dq[dq_i]),.O(ioi_dq_in[dq_i]));
end
endgenerate

 

 

 

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7 Replies
Highlighted
Teacher
Teacher
6,896 Views
Registered: ‎09-09-2010

"I am designing DDR2 controller from scratch."

BAD PLAN!
Use the CoreGen IP.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Highlighted
Visitor
Visitor
6,891 Views
Registered: ‎11-10-2011

I don't want to use the core generator.....

 

I interested in answer that will help me to use DQS for reading the DATA from memory
 where can i find material about how to use DQS as a clock for sampling DQ??? 

 

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Highlighted
Xilinx Employee
Xilinx Employee
6,880 Views
Registered: ‎10-23-2007

You might want to take a look at the Northwest Logic soft phy for DDR2 available for the Spartan-6:

 

  http://www.xilinx.com/products/intellectual-property/1-1MFEDB.htm

 

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Highlighted
Historian
Historian
6,863 Views
Registered: ‎02-25-2008


@rcingham wrote:
"I am designing DDR2 controller from scratch."

BAD PLAN!
Use the CoreGen IP.

For the experienced FPGA person, it's not a bad plan, and using the CoreGen core might be more problematic.

 

For the newbie? Use MIG or whatever.

----------------------------Yes, I do this for a living.
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Highlighted
Teacher
Teacher
6,848 Views
Registered: ‎09-09-2010

I am aware of 2 small problems with the MIG DDR2 SDRAM cores for Virtex-4 and Virtex-5 (no experience of Spartan versions):
long latency between User/Application Interface and memory interface;
discrepancies between User/Application Interfaces of the 2 families' cores.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Highlighted
Historian
Historian
6,842 Views
Registered: ‎02-25-2008


@rcingham wrote:
I am aware of 2 small problems with the MIG DDR2 SDRAM cores for Virtex-4 and Virtex-5 (no experience of Spartan versions):
long latency between User/Application Interface and memory interface;
discrepancies between User/Application Interfaces of the 2 families' cores.

You are right about the latency -- it's borderline ridiculous. As if Xilinx meant it as a joke.

----------------------------Yes, I do this for a living.
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Highlighted
Visitor
Visitor
6,706 Views
Registered: ‎07-22-2012

I recently use iosedes2 is also experiencing this problem, I use kdqs to take dq signal, but the final of data until the next read will send, someone can provide information to my reference !

 

use Dqs + bufio2 can be achieved ???

 

thank you

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