05-19-2010 11:47 AM
05-19-2010 03:41 PM
I'm not familiar with the board, but that schematic looks messed up to me. It's possible that it is hooked up correctly to the memory controller (in spite of the net labels), but I would have to see the FPGA code to determine that. Are you supposed to write your own FPGA code, or does the board come ready to roll?
05-21-2010 07:30 PM
It seems fine to me. Well it's a bit confusing that it would be logical to call the dqs signal for the first memory ldqs0 and udqs0, and for the second one ldqs1 and udqs1. In this design U13 connected to the nets ldqs0 and ldqs1 and U12 to udqs0 and udqs1. What's important is that the bits in a byte lane and corresponding dqs signals match: ldqs0 for d0-7, ldqs1 for d8-15, udqs0 for d16-23 and udqs1 for d24-31.
I assume the designer thought it's logical to name the dqs signals for the 4 bytes of the data bus in the system so the lower 16bit word connected to U13 got ldqs (lower dqs) 0 and 1 and the upper 16 bits connected to U12 got udqs 0 and 1.
05-24-2010 06:13 AM
Bagoj is correct. The ldqs/udqs usage was simply a naming convention of the schematic designer. If you look at MIG's output for a 32-bit interface, there is no lower or uppder designation. It is simply DQS, DQS, DQS, DQS. So, in this implementation, the schematic designer chose
ldqs0 = DQS
ldqs1 = DQS
udqs0 = DQS
udqs1 = DQS
Bagoj states the key -- each byte lane and respective dqs must match.
Also, if you are comparing the default MIG output to this board, you will notice that the pinouts do not match. The default MIG output is not the only legal pinout for a MIG controller on Spartan-3A. MIG defines a set of I/O rules by which you could define your own pinout if you choose. This board was designed prior to the MIG defaults being set for this device/package, so the designers picked a pinout based on MIG requirements.
Some ISE 9.2 examples using MIG are posted for this board at www.em.avnet.com/spartan3a-dsp --> Support Files & Downloads.
05-24-2010 02:21 PM
05-24-2010 02:30 PM
That is the wrong I/O standard for the dqs/dqs_n pins. It should be differential SSTL, not LVDS. I'm using Virex5, but that is the DDR2 SDRAM standard, so I assume it's the same for your part.
NET "DDR2_DQS[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
NET "DDR2_DQS_N[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
05-25-2010 12:44 AM
As I'm new to all this I'm finding it difficult to find any documents detailing the problem. I just ran the MIG tool with settings for a 1800A FPGA and Micron memory device, all availabel from the pull down menues within MIG. There is no setting that I could see to set differnat I/O types so I assumed that MIG would configure the output using the information entered in the GUI.
Are you suggesting that I need to edit the UCF file first before trying to implement the design in ISE?
05-25-2010 01:20 AM
Just checked the UCF that MIG generated for the DDR2 interface and the I/O standards for these signal are:
"cntrIO_ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_I
So I'm still sratching my head !!!
05-25-2010 09:40 AM
Yes, I included it. Obviously I'm doing something wrong as I using only files that are generated from MIG in the example folder that is generated. Avnet did a Speedway course on DDR2 interface using the same DEV board that I have so I'm trying to get hold of the 'labs' that were used in the course but haven't been able to get them yet.
Anyway, I'll have another go tonight and see if I can make any head way.
05-25-2010 11:32 AM