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Observer bazzae123
Observer
7,602 Views
Registered: ‎07-14-2009

DDR2 Interface, Please help before head explodes

Hi Guy's, Please can somebody help me before the stress gets the better of me. I'm trying to implement a DDR2 interface using a 1800A DSP and I'm been looking at the DEV board design for guidance. http://www.xilinx.com/support/documentation/boards_and_kits/Sp3A-DSP-1800A-Starter-Schematic-Rev1.pdf On sheet 8 it shows a implementation using two Micron DDR2 devices where all the signal names tie up with the DDR2 pin names apart from U13 - B7,A8 which are called LDQS 1 and U12 - F7,E8 which are called UDQS 0. Now,it appears that these two sets of signals are swapped over as U13 are mainly of the Group 0 name set and U12 are mainly of the group 1 set and not forgetting the off page connector names don't match the pin names, is this correct? If any body could help me out I would really appreciate it as this is my first DDR design. Bazza
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12 Replies
Explorer
Explorer
7,590 Views
Registered: ‎09-11-2007

Re: DDR2 Interface, Please help before head explodes

I'm not familiar with the board, but that schematic looks messed up to me.  It's possible that it is hooked up correctly to the memory controller (in spite of the net labels), but I would have to see the FPGA code to determine that.  Are you supposed to write your own FPGA code, or does the board come ready to roll?

 

Barry

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Observer bazzae123
Observer
7,564 Views
Registered: ‎07-14-2009

Re: DDR2 Interface, Please help before head explodes

Hi Barry,

 

Yes, the board comes ready to role.

 

Bazza

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Explorer
Explorer
7,558 Views
Registered: ‎09-11-2007

Re: DDR2 Interface, Please help before head explodes

Well, I would ignore those net labels on the schematic - they look wrong to me.

 

Barry

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Contributor
Contributor
7,525 Views
Registered: ‎04-03-2009

Re: DDR2 Interface, Please help before head explodes

Hi!

 

It seems fine to me. Well it's a bit confusing that it would be logical to call the dqs signal for the first memory ldqs0 and udqs0, and for the second one ldqs1 and udqs1. In this design U13 connected to the nets ldqs0 and ldqs1 and U12 to udqs0 and udqs1. What's important is that the bits in a byte lane and corresponding dqs signals match: ldqs0 for d0-7, ldqs1 for d8-15, udqs0 for d16-23 and udqs1 for d24-31.

I assume the designer thought it's logical to name the dqs signals for the 4 bytes of the data bus in the system so the lower 16bit word connected to U13 got ldqs (lower dqs) 0 and 1 and the upper 16 bits connected to U12 got udqs 0 and 1.

 

HTH,

Bagoj

 

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Voyager
Voyager
7,481 Views
Registered: ‎10-01-2007

Re: DDR2 Interface, Please help before head explodes

Bagoj is correct.  The ldqs/udqs usage was simply a naming convention of the schematic designer.  If you look at MIG's output for a 32-bit interface, there is no lower or uppder designation.  It is simply DQS[0], DQS[1], DQS[2], DQS[3].  So, in this implementation, the schematic designer chose

  ldqs0 = DQS[0]

  ldqs1 = DQS[1]

  udqs0 = DQS[2]

  udqs1 = DQS[3]

 

Bagoj states the key -- each byte lane and respective dqs must match.

 

Also, if you are comparing the default MIG output to this board, you will notice that the pinouts do not match.  The default MIG output is not the only legal pinout for a MIG controller on Spartan-3A.  MIG defines a set of I/O rules by which you could define your own pinout if you choose.  This board was designed prior to the MIG defaults being set for this device/package, so the designers picked a pinout based on MIG requirements.

 

Some ISE 9.2 examples using MIG are posted for this board at www.em.avnet.com/spartan3a-dsp --> Support Files & Downloads.

 

Bryan

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Observer bazzae123
Observer
7,462 Views
Registered: ‎07-14-2009

Re: DDR2 Interface, Please help before head explodes

Thanks guy's for all your help on this one. I eventually found this was correct but haven't had chance to post anything yet as I have been going through the MIG generator to try and understand a bit more about what going on. Also, thanks for your suggestion about looking at the Avent web site which I actually did before reading your reply as I was looking for a answer to a problem I have with MIG and trying to get a design that runs in ISE. The problem that I'm having and I haven't found a answer to yet is when I try and implement the project in ISE I get the following error message PhysDesignRules:760 - Incompatible programming for IO standard. IO standard LVDS_25 of comp cntrl0_ddr2_dqs<3> does not allow both input and output programming on the same comp. The FPGA is a 1800A-DSP and the memory is Micron MT47H32M16HR25EF the same as on the DEV board. I have no idea why the error appears so if any body could throw some light on it I may be able to sleep at some point, MIG is 3.3 Any help on this would be appreciated. Bazza
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Explorer
Explorer
7,459 Views
Registered: ‎09-11-2007

Re: DDR2 Interface, Please help before head explodes

That is the wrong I/O standard for the dqs/dqs_n pins.  It should be differential SSTL, not LVDS.  I'm using Virex5, but that is the DDR2 SDRAM standard, so I assume it's the same for your part.

 

NET  "DDR2_DQS[*]"                              IOSTANDARD = DIFF_SSTL18_II_DCI;
NET  "DDR2_DQS_N[*]"                            IOSTANDARD = DIFF_SSTL18_II_DCI;

Barry

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Observer bazzae123
Observer
7,432 Views
Registered: ‎07-14-2009

Re: DDR2 Interface, Please help before head explodes

Hi Barry,

 

As I'm new to all this I'm finding it difficult to find any documents detailing the problem. I just ran the MIG tool with settings for a 1800A FPGA and Micron memory device, all availabel from the pull down menues within MIG. There is no setting that I could see to set differnat I/O types so I assumed that MIG would configure the output using the information entered in the GUI.

Are you suggesting that I need to edit the UCF file first before trying to implement the design in ISE? 

 

Regards

 

Barry

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Observer bazzae123
Observer
7,430 Views
Registered: ‎07-14-2009

Re: DDR2 Interface, Please help before head explodes

Hi Barry,

 

Just checked the UCF that MIG generated for the DDR2 interface and the I/O standards for these signal are:

 

"cntrIO_ddr2_dqs[*]"   IOSTANDARD = DIFF_SSTL18_I

 

So I'm still sratching my head !!!

 

Regards

 

Bazza

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Explorer
Explorer
2,827 Views
Registered: ‎09-11-2007

Re: DDR2 Interface, Please help before head explodes

Is the ucf file from the MIG included in your ISE project?

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Observer bazzae123
Observer
2,821 Views
Registered: ‎07-14-2009

Re: DDR2 Interface, Please help before head explodes

Hi Barry,

 

Yes, I included it. Obviously I'm doing something wrong as I using only files that are generated from MIG in the example folder that is generated. Avnet did a Speedway course on DDR2 interface using the same DEV board that I have so I'm trying to get hold of the 'labs' that were used in the course but haven't been able to get them yet.

Anyway, I'll have another go tonight and see if I can make any head way.

Bazza

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Observer bazzae123
Observer
2,816 Views
Registered: ‎07-14-2009

Re: DDR2 Interface, Please help before head explodes

Sorted. It was down to finger trouble from me and a case of RTFM. Thanks any way guys for your help and advice. Bazza
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