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Registered: ‎04-20-2016

DDR2 registers problem/ a way for debugging on FPGA instead of simulation

I could really use some help 
I am trying to transmit a certain sequence using one ODDR2 register and receiving that same sequence through 4 IDDR2 registers they all start working at the same time, the design works well on the simulation , the transmitter transmits the sequence and it is received by all the 4 IDDR2 at the same time 

however after the implementation and uploading the code on the FPGA a constant delay of 4 clock cycles (8 bits) in two of those IDDR2 has appeared , i tried to change the differential pads of the transmitter from A3 B3 to A5 B5, the result was that one of these IDDR2 had no result while the others received the sequence at the same time
my question is, is there a way to debug on the FPGA instead of using the simulation ?


Thank you

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Xilinx Employee
Xilinx Employee
Registered: ‎06-30-2010

I am not fully sure of the setup, you have 1 ODDR2 driving to 4 IDDR2 registers on the board is that correct?


could the problem be skew in the PCB routing?


If you send a count pattern and monitor the IDDR2 outputs using Chipscope and an ILA is the count pattern recieved miss aligned?



Don’t forget to reply, kudo, and accept as solution.
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