We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor ioannis_85
Registered: ‎03-10-2013

Digilent Atlys and Video processing

Dear all,


My name is Ioannis and I am new in the world of FPGAs.

I know the basic things about VHDL.

For the last month I am trying to implement the sobel operator in the demo project that Digilent gives. (VmodCAM_Ref_VGA Demo_13).

I have made the sobel operator in VHDL and I am importing it to this project, I am progremming the board but in my monitor I can see only single colours and not frames from the VmodCamera. I think that the problems must be in the timing synconization.


Does anyone has work in a project liek this?


Thank you for your help!

0 Kudos