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Adventurer
Adventurer
2,646 Views
Registered: ‎04-04-2010

Double clock rate SRAM design

Hello,

 

I have a design that uses SRAM blocks and I would like to configure them with a single set of output registers.  This would ordinarily introduce an extra cycle of latency in a read operation. 

 

However, would it be possible for me to clock the SRAM at 100MHz whilst the rest of the system is clocked at 50MHz, and thus maintain 20ns SRAM read time (2 * 10ns) from the prespective of the rest of the system logic?  My thinking is that with a read operation, rising edges on the SRAM clock (100MHz) that coincide with rising edges on the system clock (50MHz) will have a vaild address on the bus.  The SRAM will be read 10ns later and 10ns after that the SRAM core output registers will also have been updated.  This on the following rising edge of the system clock (20ns later) valid data will be available at the registers. 

 

If this works, then I'd appreciate any comments on the following further issues:

 

1. In addition to the SRAM clock (100MHz) rising edges that coincide with the system clock (50 MHz) rising edges, there will also be SRAM clock rising edges that are mid-cycle from the perspective of the system clock.  At this time the address bus will not have valid data. Hence each other SRAM clock cycle, the output of the SRAM core and registers will be nonsense.  Since the nonsense data output does not correspond with a rising edge on the system clock this should not cause a problem, but are there any problems you see here?

 

2. How can I configure timing constraints to ignore the above issue (i.e. to accept that address bus data will not be ready each 10ns and not require this, even though the SRAM is clocked at 100MHz)?

 

3.  Is there a better way of approaching this, assuming my objective is to achive _registered_ SRAM output without any extra latency from the prespective of the 50MHz system?

 

Many thanks indeed for any help.

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1 Reply
ikerlan_fpga
Contributor
Contributor
2,633 Views
Registered: ‎05-13-2013

Hi,

 

I have not understood exactly your problem. But maybe the use of a DDR2 SDRAM device that achieve high-speed operation by transferring data on both the rising and falling edges of the clock signal would help. The memory operates using a differential clock provided by the controller. Commands are registered at every positive edge of the clock.

 

Good luck,

IKERLAN FPGA
fpga@ikerlan.es
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