Dual port RAM timing analysis

[anuroop.ekm@gmail.com]

I have designed a dual port RAM using verilog hdl. How to find the maximum frequency of operation of the RAM ? 

Timing Summary: ( ISE 14.6)
---------------
Speed Grade: -2

Minimum period: No path found
Minimum input arrival time before clock: 1.493ns
Maximum output required time after clock: 4.322ns
Maximum combinational path delay: No path found

Thanks in advance...

Regards,
Anuroop

[guillaumebres]

anuroop.ekm@gmail.com,

maybe in the 'DC/AC switching' documentations, like this one for the zc2010/2020 architectures? http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

[anuroop.ekm@gmail.com]

Thanks for the reply ...

Actually, I'm not using a core generator to create dual port ram. I have designed it myself using Verilog HDL. I want to do timing analysis of my design.

[guillaumebres]

well that works too because the tool is going to turn your code into a RAM object, which you can see in the implemented design.

You didn't mention timing analysis, but you can perform one right away and see how well your design performs