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Visitor bkishore81
Visitor
3,820 Views
Registered: ‎06-11-2010

Dynamically changing FPGA Bank IO voltage

Is it OK to change the FPGA bank voltage dynamically from one higher voltage to lower voltage (say 3.3V to 1.8V) and viceversa? If so, what will be the behaviour of the IOs when the corresponding bank voltage is set to change dynically?

 

Any thoughts?

 

Thanks and regards.

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3 Replies
Voyager
Voyager
3,815 Views
Registered: ‎05-21-2008

Re: Dynamically changing FPGA Bank IO voltage

Do you use Spartan3/6? Vcco of bank2 must be supplied all the time. If bank2's Vcco is lost, configuration data will be lost too. For other bank, you can change Vcco dynamically. The glitch I think will be on IO.

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Visitor bkishore81
Visitor
3,811 Views
Registered: ‎06-11-2010

Re: Dynamically changing FPGA Bank IO voltage

The plan is to use Spartan 3 FPGA.

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Instructor
Instructor
3,778 Views
Registered: ‎08-14-2007

Re: Dynamically changing FPGA Bank IO voltage

As suggested, stay away from banks used during configuration.  Also look through the

users guide to check on the behavior of individual IO standards.  Some input standards

are not affected by Vcco.  All output standards are affected.  LVCMOS inputs use an

input threshold based on Vcco.  LVCMOS outputs drive to Vcco when high regardless

of whether the Vcco matches the assigned standard.  If you use a Vcco other than that

specified in the iostandard, i.e. LVCMOS33 with Vcco = 1.8V, the drive capability will

not match the standard.  Generally drivers are stronger with higher Vcco, so LVCMOS33

12 mA will only drive a fraction of 12 mA when the Vcco is lowered to 1.8V.  You can

get an idea of the ratios by looking at the maximum available drive strength for each

voltage standard.

 

HTH,

Gabor

-- Gabor
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