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Visitor morppheu
Visitor
3,679 Views
Registered: ‎01-28-2010

E1 interface problem with Spartan3E S100...

Hey guys!
 
I am the only FPGA coder at my job, and I need some help. =)
 
Our product (PABX) is modular. The costumer can attach an E1 interface (MT9076B) using a expansion card.
And here is the problem.
 
I have a internal clock of 16.384MHz (50ppm) and a E1 interface(MT9076B).
The E1 have a 4.096MHz clock (regenerated from E1) and a F0 (Frame sync signal, active low).
When the E1 is installed (MT9076 chip is soldered at motherboard or through a expansion card), I use the E1 clock as master clock. One of my DCM (I have 2, Spartan3e S100) I use to generate a 2MHz clock from E1 clock.
This clock I use to send the E1 data to MT9076, aligned with F0 signal.
What I want to do is use only the internal 2.048MHz (generate from 16.384MHz clock, with DCM) and interface with E1 through a FIFO.
Here is the problem. Internal and external clock are different, so the FIFO will go underflow or overflow...
What I can do?? Use a DCM to phase lock both clocks?? But when MT9076 goes free running I will have problem anyway.

Waiting suggestions.. 

Thanks!
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1 Reply
Scholar austin
Scholar
3,661 Views
Registered: ‎02-27-2008

Re: E1 interface problem with Spartan3E S100...

m,

 

This is the classic problem with ALL synchronous telephony!


When the clocks differ, you get underflow, or overflow, and a "frame slip."

 

There are specifications for how often a frame slip is allowed (in a PABX), so go find out.

 

Make the buffer exactly some number of frames, I think exactly one frame is best, perhaps two.

 

When you slip, you should re-establish frame sync as fast as possible, so you do not cause too long an outage (or loss of voice, or data on the E1).

 

The signals should all be synchronous (the internal 16.384 MHz should be the output of a 'Stratum 4 clock', which is traking (following) the frequency of one of the E1 inpts to the system).

 

Any E1 (or T1) terminal (end-point) equipment should be using the received clock frequency to generate all outgoing clocks.  This is supposed to be the function of the terminal clock (Stratum 4).  When no input reference is available, it should fall back to +/-50 ppm ONLY.

 

http://www.raltron.com/products/pdfspecs/sync_an02-StratumLevelDefined.pdf

 

In the E1 system, the specifications are similar to the T1 (North America) specs above.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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