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Adventurer
Adventurer
7,510 Views
Registered: ‎04-09-2013

EDK xps MPMC constraint

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There is an existing microblaze design to which I need to add an extra mpmc to support a second separate block of DDR2. Got to point where XPS will generate a new netlist without errors, but was expecting additional constraints for this mpmc - LOC, RLOC etc to be added to the system.ucf file, however nothing has appeared.

 

Does this require an additional step or have I missed something?

 

##Robert

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Xilinx Employee
Xilinx Employee
14,325 Views
Registered: ‎07-11-2011

Re: EDK xps MPMC constraint

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@hillipsrb

 

That should be correct.

You can double check if DDR2 pins are listed in "ports" tab "external ports" section and if the netlist and bitgen are completed , you can verify the .pad report  for the memory pinouts.

 

-Vanitha

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: EDK xps MPMC constraint

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@hillipsrb

 

Do you use static phy or MIG phy?

 

If it is integarted MIG flow the pinout and constraints information are located in
<EDK_Project_Dir>/__xps/mig/gui/*/user_design/par/*.ucf.

 

I would suggest you to go through "MIG/MPMC Tool Flow" section of below DS643 for more details

http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_06_a/mpmc.pdf

 

Hope this helps

-Vanitha

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Adventurer
Adventurer
7,498 Views
Registered: ‎04-09-2013

Re: EDK xps MPMC constraint

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Hi Vanitha,

 

Thanks for very prompt reply. I can't answer your question about static v. MIG, as the mpmc was added by using XPS with a drag-and-drop as described in a Silica youtube video -https://www.youtube.com/watch?v=ZBSF2x482r4

(Silica are an authorised UK Xilinx dist. so it seems likely that the video is accurate).

 

I was hoping/expecting that XPS would automatically generate constraints where needed - there is a comment on p43 of the document DS643 'The EDK XPS tool manages this process, when using the integrated MIG GUI Flow, by managing the MIG UCFconstraints automatically after MIG pinout selection.' but maybe this is wrong?

 

##Robert

 

 

 

 

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Xilinx Employee
Xilinx Employee
14,326 Views
Registered: ‎07-11-2011

Re: EDK xps MPMC constraint

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@hillipsrb

 

That should be correct.

You can double check if DDR2 pins are listed in "ports" tab "external ports" section and if the netlist and bitgen are completed , you can verify the .pad report  for the memory pinouts.

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Adventurer
Adventurer
7,452 Views
Registered: ‎04-09-2013

Re: EDK xps MPMC constraint

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Hi Vanitha,

 

I've checked that the ports are listed in the external section under the ports tab in XPS but having seached the whole of the EDK project folder tree, there has not been any additional constraints generated for the new mpmc so I'm coming to the conclusion that maybe this has to be done separately. DS643 talks about running MIG and then importing the constraints into XPS so I guess I'll need to look further into that. I guess this makes sense in a way because until the actual FPGA pins for the phy are selected, presumably it's not possible to generate any constraints.

 

Thanks for your suggestions and advice.

 

##Robert

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