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Visitor kdpatinos
Visitor
2,822 Views
Registered: ‎03-15-2017

EMC test in SPARTAN6 -- EMI issues

Hi, 

I am using a SPARTAN6 FPGA and the PCB has 4 layers. I have problems with the EMI response of my design. I'm using all of recommendation with UCF and with the use of spread spectrum CLK. 

 

######################
# Timing Constraints #
######################

##### Grouping Constraints #####
NET CLKIN_I TNM_NET = clk50_grp;

##### Clock Period Constraints #####
TIMESPEC TS_PER_CLK50 = PERIOD "clk50_grp" 20.0 ns;

#######################
# Pin LOC Constraints #s
#######################

NET CLKIN_I      LOC = "P84";
NET RST          LOC = "P138";

NET led          LOC = "P39";

NET "gpio_io<15>" LOC="P102" | IOSTANDARD = LVCMOS33;
NET "gpio_io<14>" LOC="P101" | IOSTANDARD = LVCMOS33;
NET "gpio_io<13>" LOC="P99" | IOSTANDARD = LVCMOS33;
NET "gpio_io<12>" LOC="P98" | IOSTANDARD = LVCMOS33;
NET "gpio_io<11>" LOC="P95" | IOSTANDARD = LVCMOS33;
NET "gpio_io<10>" LOC="P94" | IOSTANDARD = LVCMOS33;
NET "gpio_io<9>" LOC="P93" | IOSTANDARD = LVCMOS33;
NET "gpio_io<8>" LOC="P92" | IOSTANDARD = LVCMOS33;
NET "gpio_io<7>" LOC="P88" | IOSTANDARD = LVCMOS33;
NET "gpio_io<6>" LOC="P85" | IOSTANDARD = LVCMOS33;
NET "gpio_io<5>" LOC="P83" | IOSTANDARD = LVCMOS33;
NET "gpio_io<4>" LOC="P82" | IOSTANDARD = LVCMOS33;
NET "gpio_io<3>" LOC="P81" | IOSTANDARD = LVCMOS33;
NET "gpio_io<2>" LOC="P80" | IOSTANDARD = LVCMOS33;
NET "gpio_io<1>" LOC="P79" | IOSTANDARD = LVCMOS33;
NET "gpio_io<0>" LOC="P78" | IOSTANDARD = LVCMOS33;

NET "gpio_io<15>" SLEW = SLOW;
NET "gpio_io<14>" SLEW = SLOW;
NET "gpio_io<13>" SLEW = SLOW;
NET "gpio_io<12>" SLEW = SLOW;
NET "gpio_io<11>" SLEW = SLOW;
NET "gpio_io<10>" SLEW = SLOW;
NET "gpio_io<9>" SLEW = SLOW;
NET "gpio_io<8>" SLEW = SLOW;
NET "gpio_io<7>" SLEW = SLOW;
NET "gpio_io<6>" SLEW = SLOW;
NET "gpio_io<5>" SLEW = SLOW;
NET "gpio_io<4>" SLEW = SLOW;
NET "gpio_io<3>" SLEW = SLOW;
NET "gpio_io<2>" SLEW = SLOW;
NET "gpio_io<1>" SLEW = SLOW;
NET "gpio_io<0>" SLEW = SLOW;

 CLK_GEN

//////////////////////////////////////////////////////////////////////////////*/


module matrix_clkgen (
  CLKIN,
	RST,
	CLKFX
	);

  input		CLKIN;
	input		RST;
	output	CLKFX;			//CLKFX => BUFG => "CLKFX" output
  
  wire  [2:0] STATUS;
  wire	CLKGEN_LOCKED;	  		//Connected to spread spectrum locked signal
  wire  RST_DCM;
  
  assign RST_DCM = RST | (STATUS[2] & ~CLKGEN_LOCKED);
  
	DCM_CLKGEN    #(
		.CLKIN_PERIOD (20.000),
		.SPREAD_SPECTRUM ("CENTER_HIGH_SPREAD"),
 		.CLKFX_MD_MAX("4.1"),
 		.CLKFX_MULTIPLY	(4),
 		.CLKFX_DIVIDE	(1) )	
	dcm_clk (
		.CLKIN   	(CLKIN),
		.FREEZEDCM (1'b0),
		.PROGDATA	(1'b0),
		.PROGEN 	(1'b0),
		.PROGCLK	(1'b0), 
		.RST     	(RST_DCM),
		.CLKFX   	(CLKFX_DCM),
		.LOCKED  	(CLKGEN_LOCKED),
		.STATUS(STATUS)
		);
   


	BUFG 	clkfx_bufg 	(.I(CLKFX_DCM),  .O(CLKFX) ) ;

endmodule

 My external CLK is a ASDMB-50.000MHZ-LY-T.

I show the EMC results of my design:EMC Results

 As you can see, It show a 50MHz harmonic, since 600MHz to 1GHz. Also you can compare with the FCC class B limit (red line). I measure with near field test probe and I detect that the FPGA is the main source. All pins has the same noise.

 

I appreciate your help if I am missing something in the UCF or in the configuration of the DCM CLK. 

Thanks 

Kevin Patino
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2 Replies
Xilinx Employee
Xilinx Employee
2,769 Views
Registered: ‎09-05-2007

Re: EMC test in SPARTAN6 -- EMI issues

Given that you are using a 50MHz clock source then it should be no surprise to see that there are spectral components with 50MHz spacing. It looks like you are internally running a 200MHz clock but it would be interesting to know the most common toggle rates of logic and signal especially the I/O; my guess is that you will find a lot of that switching around the 50MHz rate again. In other words, it’s not so much the clock itself but everything else that is contributing to the EMI. Remember that energy is consumed when logic changes states and those demands will get back into the power rails unless there is enough suitably chosen decoupling capacitors close to the device. EMI not only requires an energy source it also requires an antenna so it’s rarely radiating directly from the silicon; more likely the ‘antennas’ connected to the silicon.

 

Spread spectrum clocks, as the name suggests, will have the effect of spreading the clock by some amount relative to a nominal frequency. This in turn will spread the spectrum of the clock across a range; reducing the energy at the nominal frequency and distributing it across the range (i.e. it does not eliminate that energy). Looking at the specification in DS162 we can work out that the spread of your 200MHz clock will be about ±9MHz which will equate back to about ±2MHz at 50MHz. As such the harmonics are being spread over 4MHz but will still make them distinct when spaced 50MHz apart.

 

If I were you, I would first convince myself that the spread spectrum scheme was really enabled by deliberately turning it off (i.e. set SPREAD_SPECTRUM to NONE) and then observing the effect on the spectrum. Do all the ‘spikes’ look sharper but higher? Given that these are harmonics then it would be useful to focus on the fundamentals at 50MHz and 200MHz and compare those too.

 

If you convince yourself that spread spectrum is doing its job then you will need to look into ways of further reducing EMI. You could look into implementing a soft spread spectrum to increase spread but you would probably achieve more by doing more to stagger activity within your design and I/O so that you get less of a regular ‘beat’ with the same 50MHz alignment. For example, you could consider using more than one DCM_CLKGEN to create multiple spread spectrum clocks; even if these had the same nominal frequency they would have no phase relationship and neither would the switching of the logic they serviced. Likewise, stagger clock enables to different circuits so they don’t all switch on the same clock edge (e.g. the same 4th clock edge of the 200MHz clock is a 50MHz ‘beat’).

 

I hope some of this helps. I would be interested to see your spectrum with spread spectrum clock disabled to see the difference.  

Ken Chapman
Principal Engineer, Xilinx UK
2,397 Views
Registered: ‎04-17-2015

Re: EMC test in SPARTAN6 -- EMI issues

Hi,

 

 

maybe you see ringing on GPIO-pins while switching?

 

you could try to reduce the oscillation with ucf-statements like:

 

NET "gpio_io<15>" LOC="P102" | IOSTANDARD = LVCMOS33 | DRIVE = 6;

 

 

Simon

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