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Newbie
Newbie
7,025 Views
Registered: ‎10-08-2009

ERROR: [HD-DB 2] Could not open new netlist - please see the console for details

Hi all, I am having the mentioned problem while trying to do a post-synthesis from Xilinx. The said problem occurred in the PlanAhead windows; no error in Xilinx ISE. Below is the console information:

 

 

Command> source {C:/Users/Lee Zhi Chien/Desktop/TESTVHDL/i8051/pa.fromNetlist.tcl}
# hdi::project new -name i8051 -dir C:/Users/Lee Zhi Chien/Desktop/TESTVHDL/i8051/patmp -netlist i8051_top.ngc -search_path {C:/Users/Lee Zhi Chien/Desktop/TESTVHDL/i8051}
INFO: [HD-EDIFIN 0] Parsing Edif File '.\.HDI-PlanAhead-4728-LeeZhiChien-PC\ngc2edif\i8051_top.edif'
INFO: [HD-EDIFIN 1] Finished Parsing Edif File '.\.HDI-PlanAhead-4728-LeeZhiChien-PC\ngc2edif\i8051_top.edif'
WARN: [HD-EDIFIN 3] No cell is specified in file 'i8051_top.ngc'
ERROR: [HD-DB 2] Could not open new netlist - please see the console for details.

 

I tried pre-synthesis and there is no error; I can do pins mapping.

 

Message Edited by zhichien on 10-08-2009 01:48 AM
ZC

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Xilinx ISE 11.1
PlanAhead 11.1
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6 Replies
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Anonymous
Not applicable
6,837 Views

I am getting exactly the same error/issue and there seems to be no answer on forum. I tried playing  with top level and module files, but no use. ISE console says synthesis successful.

 

Pradeep Shinde

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Newbie
Newbie
6,834 Views
Registered: ‎10-08-2009

Hi, I have already done my project and not going to use the board any more. I have less clue in the solution. You would want to try make sure the TOP file (in my case) has all signals being assigned properly. Also try to re-create the project and add in the .vhd files and recompile. Good luck.
ZC

---------------------------------------

Xilinx ISE 11.1
PlanAhead 11.1
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Historian
Historian
6,832 Views
Registered: ‎02-25-2008

There are spaces in the project's path name!

 

Fix that, and it might work ...

----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
6,827 Views

I rechecked TOP module, all the signals used in lower module are defined. No spaces in the project's path name (as shown in console - where else to check/correct this?). ISE console declares:
"Process "Synthesis" completed successfully"

 

Just last week there was no such issue with this project. I reviewed and rewrote the only added file which is certainly not a culprit. Making a new project  with the sme vhd files does not look logical. Anyway, I will try this as well.

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Historian
Historian
6,810 Views
Registered: ‎02-25-2008


shinde wrote:

I rechecked TOP module, all the signals used in lower module are defined. No spaces in the project's path name (as shown in console - where else to check/correct this?). ISE console declares:
"Process "Synthesis" completed successfully"

 

Just last week there was no such issue with this project. I reviewed and rewrote the only added file which is certainly not a culprit. Making a new project  with the sme vhd files does not look logical. Anyway, I will try this as well.


Ummm, look at your first post in this thread:

 


hdi::project new -name i8051 -dir C:/Users/Lee Zhi Chien/Desktop/TESTVHDL/i8051/patmp -netlist i8051_top.ngc -search_path {C:/Users/Lee Zhi Chien/Desktop/TESTVHDL/i8051} 

 


 C:/Users/Lee Zhi Chien/Desktop/TESTVHDL/i8051/patmp contains at least two spaces ...
----------------------------Yes, I do this for a living.
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Anonymous
Not applicable
6,807 Views

That posting is by someone else (who experienced it earlier). I am a second person posting the same issue.
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