03-22-2011 01:19 PM
I am trying to simulate MCB on spartan 6 to read and write from memory.
I have chosen MT47H16M16XX-3 part for the memory in core generator tool.
When i try to simulate using ISIM i get the following errors in the simulation model:
ERROR:Line 159: Size mismatch in mixed language port association, verilog port ba
ERROR: Line 160: Size mismatch in mixed language port association, verilog port addr
I changed the number of bits for ba,addr in the header file for the simulation model ,the errors are vanished. But does not it mean that the memory is not set up properly and the other values like column address bits, row address bits , cas latency,ras latency might be different than what has to be used?
Would really appreciate if some one can help.
10-18-2011 01:06 AM
I have exactly the same problem. I used ISE 13.2 and generated a MCB design. When I try simulating the "user design" folder contents in ISIM, I get the below error
"Line 129: Size mismatch in mixed language port association, verilog port addr"
As far as I understand, the "ifdef" statements in the ddr model defines the addr width as 13 bits (in 16 bit wide DDR bus)
however the MIG generated files expects it to be 14 bits.
can you please guide me about solving this problem? I don't think that changing ddr model parameters manually should be a good solution.
The memory part I used is MT41J128M16XX-187E
thank you very much for your help
10-18-2011 03:14 AM
I just tried running the simulation in batch mode and everything functions correctly. It seems that while forming the project in ISE manually, I messed up at some point (I only added the project files and didn't do any extra setting configuration).
Well, since I have a working design, I can compare the problematic flow and find the problem. If I can I'll write it back here.
ps: for running the ISIM in batch mode in Ubuntu, the following link may be handy
10-18-2011 04:05 AM
I have noticed that in batch mode, ISIM gets the compilation commands from a project file *.prj The ddr models are compiled with extra options as below
verilog work ./ddr3_model_c1.v -d x2Gb -d sg187E -d x16 -i ./
One can see the "-d x16" parameter. I think that when I manually generated the project I wasn't able to (and still don't know how to) set the ddr model to 2Gb and 16bit wide data bus option.
I would be happy if someone can tell me how to do this.
thanks a lot