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Visitor
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Registered: ‎02-12-2014

ERROR:Place:1108

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Hi,

I'm using  ISE 14.7 in the design of an XC6SLX9-2tqg144.
During map I get this error message:

ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <SpiMcuSCLK> is placed at site <P120>. The corresponding BUFG
   component <SpiMcuSCLK_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y9>. There is
   only a select set of IOBs that can use the fast path to the Clocker buffer,...
  
  OK, I have figured out that P120 is IO_L62N_VREF_0, and that this is not a good choice for a clock input.
 
  However, some years ago, a HW-designer placed a single-ended clock input at P120 = IO_L62N_VREF_0.
 
  How can I make the "best clock performance" out of this situation?
 
  Regards
  Trygve

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010

Re: ERROR:Place:1108

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Hi Trygve,

 

Here is the constraint to LOC the BUFG.

INST "SpiMcuSCLK_BUFGP/BUFG" LOC = "BUFGMUX_X3Y6";

 

Looking at the snapshot of fpga editor i see the signal is spread between the top and bottom half of the device.

I would suggest locking the BUFMUX instance to the tophalf BUFGMUX(highlighted in the snapshot) as defined in the above constraint.

 

Spartan6.png

Refer to ug382 for spartan 6 clocking details.

 

 

I hope this helps.

 

Regards,

Achutha

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010

Re: ERROR:Place:1108

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Hi,

There are few clocking limitations with respect to Spartan-6 device.
In order resolve the issue,
1. I would first recommend using the CLOCK_DEDICATED_ROUTE constraint given in the error message and see the clocking placement.
2. Check the placement of the BUFGMUX with respect to the IO locked
3. If the clock loads are spread across the device , try to lock the BUFGMUX element to upper BUFGMUX and remove the CLOCK_DEDICATED_ROUTE constraint.

Regards,
Achutha
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Moderator
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Registered: ‎01-16-2013

Re: ERROR:Place:1108

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Hello,

 

IO site is P120 which corrospond to BANK0. {refer below snapshot}

s6_1.PNG

 

You cannot use BUFGMUX_X2Y9. refer below snapshot for BANK0 and corrosponding BUFGMUX location.

 

s6_2.PNG

 

Thanks,

Yash

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: ERROR:Place:1108

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Hi,

 

The reason for the error is that you are not using GCLK pin to drive the BUFG.

 

Check this thread http://forums.xilinx.com/t5/New-Users-Forum/should-we-use-a-pin-named-GCLK-just-as-clock/td-p/270050

 

Also this AR helps http://www.xilinx.com/support/answers/46750.html 

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor
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Registered: ‎02-12-2014

Re: ERROR:Place:1108

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OK, so I used the attribute  NET "SpiMcuSCLK" CLOCK_DEDICATED_ROUTE = FALSE;
  and did synthesis/implement over again.  As before the map tool selected BUFGMUX_X2Y9  for the SpiMcu_SCLK (P120) net
  The fanout of SpiMcu_SCLK_BUFG is shown in the figure below.  I understand your suggestion such that you now advice me to accept using BUFGMUX_X2Y9,
  and to lock to this position in the UCF-file. OK could you be so kind s to share this lock attribute/command syntax with me?
 
  Regards Trygve

 

Fpga_Editor_2014-06-11_cropped_twice.jpg

 

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Moderator
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Registered: ‎01-16-2013

Re: ERROR:Place:1108

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Hello,

 

OK, so I used the attribute  NET "SpiMcuSCLK" CLOCK_DEDICATED_ROUTE = FALSE;
  and did synthesis/implement over again.  As before the map tool selected BUFGMUX_X2Y9  for the SpiMcu_SCLK (P120) net
  The fanout of SpiMcu_SCLK_BUFG is shown in the figure below.  I understand your suggestion such that you now advice me to accept using BUFGMUX_X2Y9,

 

--> I dont understand this statement. Could you please provide more detail?

 

could you be so kind s to share this lock attribute/command syntax with me?

 

--> Refer this UG: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf (Page 142 LOC constraint).

 

Thanks,

Yash

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010

Re: ERROR:Place:1108

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Hi Trygve,

 

Here is the constraint to LOC the BUFG.

INST "SpiMcuSCLK_BUFGP/BUFG" LOC = "BUFGMUX_X3Y6";

 

Looking at the snapshot of fpga editor i see the signal is spread between the top and bottom half of the device.

I would suggest locking the BUFMUX instance to the tophalf BUFGMUX(highlighted in the snapshot) as defined in the above constraint.

 

Spartan6.png

Refer to ug382 for spartan 6 clocking details.

 

 

I hope this helps.

 

Regards,

Achutha

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Visitor
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Re: ERROR:Place:1108

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Thanks Achutha,
  I agree that INST "SpiMcuSCLK_BUFGP/BUFG" LOC = "BUFGMUX_X3Y6"; makes the best out of my situation with a clock input at P120.
  Minor comment: Using the LOC attribute I tried removing the CLOCK_DEDICATED_ROUTE = FALSE, then the ERROR:Place:1108 reappeared again.
  So now I run with both INST "SpiMcuSCLK_BUFGP/BUFG" LOC = "BUFGMUX_X3Y6"; and NET "SpiMcuSCLK" CLOCK_DEDICATED_ROUTE = FALSE;
  And accept this as my solution.
  
  Regards Trygve

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Instructor
Instructor
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Registered: ‎07-21-2009

Re: ERROR:Place:1108

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Keep in mind the following:

 

  • Using the CLOCK_DEDICATED_ROUTE = FALSE directive does not affect the layout, placement, or performance of your design in any manner whatsoever.  Its only purpose is to reduce an error message to a warning message.
  • If the clock source for the input clock is a typical oscillator -- and has no particular timing or phase relationship to input data to the device -- then using using a non-GCLK input pin for the clock should be perfectly acceptable.

Without more insight into how your design uses the buffered clock, it is difficult to conclude whether or not your clock pin assigment is a problem for your design.

 

-- Bob Elkind

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Visitor
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Re: ERROR:Place:1108

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OK, thank you for the useful reminder/specification.
 
  Regards Trygve

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