Elements required to load configuration data from SPI flash after power up (Spartan 6)

[@alxtrnk]

Hi to all. 

I would like to know what I exactly need to load a bitstream + C-code from an external flash memory to the FPGA after power up the FPGA.

I am using a custom board with Spartan-6 LX45T. Data must be retained after power down and power up FPGA so we use a flash memory (S25FL256S by Spansion). This flash memory is not attached to JTAG chain, and it is not supported by Spartan 6 to carry out indirect programming. So I have to use a specific software to load .bin and .srec files into flash (my system is composed of one Microblaze + Logic). This is done by Ethernet (UDP), and apparently, the process is correctly done. But after power up again FPGA, nothing is loaded from Flash.

I am a newbie with this so, sorry if I say something stupid.. During design phase I have not required to save the code on the Flash, but now I need it , and it seems that it is not as easy as I thought. So I would need a little explanation about what I would need to carry this out. So these are my doubts:

1. Do I need a Microblaze system with an AXI Quad SPI Core to load data from Flash after power it up??

2. If yes, how could it be possible to load a bitstream without a Microblaze system (only VHDL code)??

3. If an AXI quad SPI core is required, should it be configured as Master or Slave?? I have tried as Master and I get this error during synthesis (Error on EXT_SPI_CLK signal):

      Why this external SPI clock should be connected??? I am only using the following signasl which are part of the SPI communication. Do i need something more??:

4. Is the use of "special" primitives like startup_spartan6 required to get what I want??

5. Do I have to configure linker script in a "special" way to allow boot from Flash??

Many thanks in advance for your support. 

Regards.

[iguo]

Hi, if you connect the hardware correctly and have a proper CCLK, it's a possibility that this flash cannot work with S6.
Flash listed for indirect programming is not only for 'indirect programming' but also hareware-compliant. Those listed in the table are flashes been tested and verified on Hardware. We cannot guarantee the other flashes work with Xilinx FPGAs.
Try to read the status word after 'configuration', if only DCM/PLL and DCI and INIT_B asserted, it's very likely that S6 cannot identify the data from this flash so it keeps its intial state. This is cannot solved by adding some internal primitive or IP, FPGA itself cannot boot up to use any of the internal logic at all.

Thanks,
Ivy

[@alxtrnk · Accepted solution]

Hi @iguo.

Many thanks for your answer. It seems there is a HW problem in the board. Flash memory has been correctly loaded on similar boards so it can work with Spartan 6 family, but i am looking for HW problems because it is not working on this board. 

Many thanks for your answer. I close the post. 

Regards.