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Visitor lenz19
Visitor
9,543 Views
Registered: ‎06-19-2009

FDRSE Spartan 3A - Active high/low set/reset

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Hi,

 

I have to instantiate two FDRSE elements in my VHDL-Code.

 

FDRSE1 should have active-high set/reset.

FDRSE2 should have active-low  set/reset.

 

This is the instantiation code from the Libraries Guide:

 

FDRSE_inst : FDRSE
generic map (
INIT => '0') -- Initial value of register ('0' or '1') 
port map (
                  Q    => Q,      -- Data output
                  C    => C,      -- Clock input
                  CE => CE,    -- Clock enable input

                  D   => D,      -- Data input
                  R   => R,      -- Synchronous reset input
                  S   => S       -- Synchronous set input
);

 

In this instantiation code, there is no possibility to configure the set/reset polarity.

 

My two questions are:

 

1. How to instantiate a FDRSE with active-high set/reset

2. How to instantiate a FDRSE with active-low  set/reset

 

Thanks in advance,

Mark Lenz

 

 

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Xilinx Employee
Xilinx Employee
11,873 Views
Registered: ‎01-03-2008

Re: FDRSE Spartan 3A - Active high/low set/reset

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The methodology that bassman59 and I have both told you to use is exactly how you get to use the "free programmable invertor" on the control lines in Spartan-3.  There is absolutely no other way to do it.

 

The "SR" pin on the CLB means "Set or Reset".  The "REV" pin on the CLB is the "REVerse" functionality of the SR pin.

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6 Replies
Historian
Historian
9,541 Views
Registered: ‎02-25-2008

Re: FDRSE Spartan 3A - Active high/low set/reset

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You could put an inverter on the set/reset signal.

 

Why instantiate? Just infer the flop.

 

-a

----------------------------Yes, I do this for a living.
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Visitor lenz19
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Registered: ‎06-19-2009

Re: FDRSE Spartan 3A - Active high/low set/reset

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Thanks for your reply but this does not answer my question.

 

How to instantiate these two FDRSE ?

 

 

Regards 

 

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Xilinx Employee
Xilinx Employee
9,521 Views
Registered: ‎01-03-2008

Re: FDRSE Spartan 3A - Active high/low set/reset

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What bassman59 said to do is what you need to do.  Add an inverter on the SET and RESET nets that connect to the FDRSE that you want to have active low inputs. 

 

set_b    <= NOT set;

reset_b <= NOT reset;

 

The invertor will be merged into the CLB slice by the ISE software.

Message Edited by mcgett on 06-19-2009 12:00 PM
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Visitor lenz19
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Registered: ‎06-19-2009

Re: FDRSE Spartan 3A - Active high/low set/reset

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mcgett wrote:

 

The invertor will be merged into the CLB slice by the ISE software.

 

Message Edited by mcgett on 06-19-2009 12:00 PM


 

That's the point. I don't want to infer extra inverter logic in the CLB. I want the inverter for free. 

 

In the Storage Elements Section of the User Guide for Spartan it is statet that

"All signals have programmable polarity; the default active-High function is described."

 

So, I am looking for a way to configure the polarity of the set/reset signals of a FDRSE.

 

There is a Flip Flop input called 'REV'.  According to the User Guide this input is a

"CLB input for opposite of SR". Could this input configure the polarity of the set/reset signals ?

 

Thanks for your contribution.

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Xilinx Employee
Xilinx Employee
11,874 Views
Registered: ‎01-03-2008

Re: FDRSE Spartan 3A - Active high/low set/reset

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The methodology that bassman59 and I have both told you to use is exactly how you get to use the "free programmable invertor" on the control lines in Spartan-3.  There is absolutely no other way to do it.

 

The "SR" pin on the CLB means "Set or Reset".  The "REV" pin on the CLB is the "REVerse" functionality of the SR pin.

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Visitor lenz19
Visitor
9,495 Views
Registered: ‎06-19-2009

Re: FDRSE Spartan 3A - Active high/low set/reset

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Thank you for your patience, I appreciate this.

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