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Observer
Observer
6,838 Views
Registered: ‎03-04-2011

FIFO

HI everybody,

 

                        I have a query on FIFO generation, Please guide me...

I has to generate a FIFO which can store a 1024 locations and also while the next block to the FIFO, FFT reads the data from FIFO then a new samples will arrive into that FIFO. I have selected the wire depth of 1024 but while i was selecting the  "Single Programmable Full threshold constant"  and the i have selected "Full Threshold Assert value" , which i want to set it as 1024 ,but its range is 3 to 1021 which 3 locations less than what i needed.   Can anybody guide me ,please...............

            

                                                                                                  Regards,

                                                                                                         Shariff.

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9 Replies
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Instructor
Instructor
6,836 Views
Registered: ‎07-21-2009

Shariff,

 

Why not decode the data_count output from the FIFO?

 

The LogiCore FIFO datasheet (DS317) explicitly mentions that there are limitations on the range of programmable threshold levels.  These limits may be based on available logic (for the Built-In FIFO) or logic/pipeline delays (if the threshold level is too close to the size (or "full" level) of the FIFO.  This is merely speculation on my part.

 

-- Bob Elkind

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Advisor
Advisor
6,834 Views
Registered: ‎10-05-2010

If you only need to know when the 1024 word FIFO is completely full, don't bother with the programmable threshold - use the "full" signal.

 

Alternatively, if your samples arrive constantly, could you use the streaming FFT interface and avoid the need for a FIFO?

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Observer
Observer
6,829 Views
Registered: ‎03-04-2011

Thanks for your reply,

                          But i am using FIFO and then FFT (Pipe line streaming).I want ot use FIFO which can store 1024 samples or more.I have generated it from xilinx core generator but with 1021 samples lenght.So please tell me how can i generate 1024 or more samples from it. Is it just by selecting the write width to 2058, i did so, then it has allowed me to select the 2053 samples?is it correct way or any other way.

 

 

                                           Regards

                                                shariff

 

                                                                   

 

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Observer
Observer
6,826 Views
Registered: ‎03-04-2011

Thanks for your reply,

                        I like to know is that a better option to take an datacount output, As while the FIFO has reached 1024 then FFT starts reading it and simultaneously next 1024 samples may also appear in the FIFO, soit might be little more than 1024, i cant expect exact value.it will be more than 1024 samples.After storing 1024 samples then with the help of Programmable flag FFT can start read from it ,mean while FIFO stores next coming saples,Ok. I am using FIFO and then FFT (Pipe line streaming).I want ot use FIFO which can store 1024 samples or more.I have generated it from xilinx core generator but with 1021 samples lenght.So please tell me how can i generate 1024 or more samples from it. Is it just by selecting the write width to 2058, i did so, then it has allowed me to select the 2053 samples?is it correct way or any other way.

 

 

                                           Regards

                                                shariff

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Instructor
Instructor
6,824 Views
Registered: ‎07-21-2009

I want ot use FIFO which can store 1024 samples or more

You can configure the FIFO as large as the target FPGA and the FIFO wizard will support.

 

If you need a FIFO to store 1236 samples, a larger FIFO (2048 samples, for example) should not cause any problems whatsoever.  Your write logic can fill the FIFO to whatever depth you would like to configure.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer
Observer
6,812 Views
Registered: ‎03-04-2011

Thanks for your reply, i will try it....
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Xilinx Employee
Xilinx Employee
6,792 Views
Registered: ‎11-28-2007

If the sample storing logic (i.e. writing to the FIFO) and the FFT (reading from the FIFO) are using the same clock, a dual port (DP) RAM should be all you need. You can divide a 2048-word DP RAM into two 1024-word ping-pong buffers and have the writing and reading logic work on the buffers alternatively.

 

 


@08220158 wrote:

Thanks for your reply,

                        I like to know is that a better option to take an datacount output, As while the FIFO has reached 1024 then FFT starts reading it and simultaneously next 1024 samples may also appear in the FIFO, soit might be little more than 1024, i cant expect exact value.it will be more than 1024 samples.After storing 1024 samples then with the help of Programmable flag FFT can start read from it ,mean while FIFO stores next coming saples,Ok. I am using FIFO and then FFT (Pipe line streaming).I want ot use FIFO which can store 1024 samples or more.I have generated it from xilinx core generator but with 1021 samples lenght.So please tell me how can i generate 1024 or more samples from it. Is it just by selecting the write width to 2058, i did so, then it has allowed me to select the 2053 samples?is it correct way or any other way.

 

 

                                           Regards

                                                shariff


 

Cheers,
Jim
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Visitor
Visitor
6,764 Views
Registered: ‎06-17-2011

@08220158 :   hii even my project is the same...but i m doing radix2 burst i/o.. can u tell me hw did u get away with the problem? if possible can u share fifo code... plz its urgent.. Thanks 

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Highlighted
6,715 Views
Registered: ‎07-12-2011

hello i too need the same design help me out its urgently needed

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