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Participant fhknapp44
Participant
2,636 Views
Registered: ‎02-25-2015

FPGA Maping Warning Message

When running the Implement Design function in ISE14.7 the Translate function works smoothly but the Map function returns the Warning "MapLib:701" and then removes the associated signal. What causes this warning message?

FHK 

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Teacher muzaffer
Teacher
2,630 Views
Registered: ‎03-31-2012

Re: FPGA Maping Warning Message

@fhknapp44 this is generally an issue when the signal has no load (ie it doesn't drive anything). You need to understand the design to see why the tool thinks this signal has no load. Are you simulating your design with this signal connected to some top level IO (directly or indirectly) ?

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