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vijji148
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Registered: ‎07-06-2016

FPGA configuration reset

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 Hi,

 

I am using spartan 6 XC6SLX45  FPGA. During configuration process, when PROG_B asserted (pulled it to low), FPGA configuration is in reset mode. By mistake if I forgot to assert the PROG_B while doing configuration what will happen ? I want to know exactly what is happening during configuration of the fpga from spi flash, and the significance of the config signals.

 

Any help would be appreciated.

 

Regards,

vijji  

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hgleamon1
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Registered: ‎11-14-2011

You've read UG380 (Spartan 6 Configuration Guide), right?

 

PROG_B is how you initiate configuration. PROG_B is taken low and then taken high. This low->high transition starts the configuration sequence. If the FPGA is the master, it will generate the CCLK and start clocking in configuration data.

 

If the FPGA is not the master then another device must provide the clock to the FPGA on the configuration port so that the configuration data can be clocked in.

 

I'm not really sure what you mean by the FPGA being in configuration reset mode.

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"That which we must learn to do, we learn by doing." - Aristotle

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kkn
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Registered: ‎01-15-2008

holding program_b low will delay the configuration and will not begin until you assert this pin

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vijji148
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Registered: ‎07-06-2016

Thank you for your response @kkn .

 

When program_b low, SPI flash is programming at the same time FPGA is in reset mode. Is there any reason FPGA to be in reset mode 

 

 

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hgleamon1
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Registered: ‎11-14-2011

What configuration mode is your FPGA-SPI pair? Is the FPGA mastering the SPI (i.e. providing the clock) or is the clock for the SPI being driven by a different clock?

 

If the FPGA is mastering then if PROG_B is low then it won't be generating the CCLK, so no configuration data will be passed between the two.

 

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"That which we must learn to do, we learn by doing." - Aristotle
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vijji148
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Registered: ‎07-06-2016

Thank you @hgleamon1 for your response.

 

The clock to SPI is providing from FT2232H not from FPGA.  

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hgleamon1
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Registered: ‎11-14-2011

Does the FT2232H also provide the configuration clock to the FPGA?

 

A diagram of what is going on could be useful.

 

My expectation is that if PROG_B is held low while the SPI is outputting data then the FPGA will not configure. If the FPGA is correctly powered and the signals are within the electrical limits of the FPGA pins then nothing bad will happen.

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"That which we must learn to do, we learn by doing." - Aristotle
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vijji148
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Registered: ‎07-06-2016

Actual my doubt is, when PROG_B is asserted and FPGA configuration is in reset mode, then how will asserting PROG_B begin configuration?

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hgleamon1
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Registered: ‎11-14-2011

You've read UG380 (Spartan 6 Configuration Guide), right?

 

PROG_B is how you initiate configuration. PROG_B is taken low and then taken high. This low->high transition starts the configuration sequence. If the FPGA is the master, it will generate the CCLK and start clocking in configuration data.

 

If the FPGA is not the master then another device must provide the clock to the FPGA on the configuration port so that the configuration data can be clocked in.

 

I'm not really sure what you mean by the FPGA being in configuration reset mode.

----------
"That which we must learn to do, we learn by doing." - Aristotle

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vijji148
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Registered: ‎07-06-2016

I gone through UG380 (Spartan 6 Configuration Guide).

 

Now, I understood . Thank you so much for your response @hgleamon1.

 

I'm not really sure what you mean by the FPGA being in configuration reset mode.

Resetting the FPGA configuration (triggers Configuration memory initialization).  

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