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Explorer
Explorer
6,423 Views
Registered: ‎05-31-2015

FPGA pins behaviour

Hello,

 

           I am using Spartan 6 FPGA in data acquisition. I communicate to ADC through FPGA , process data in FPGA , Communicate to DAC through FPGA. Individually my ADC and DAC communication works good. I drive some of input pins of DAC directly by a ramp (which is VHDL programmed) and some other pins get data read from ADC (that is read by FPGA and given to DAC). The ramp output pins work good when FPGA program reads 0 from ADC and gets noisy when any data other than 0 is read.

 

           I went through my program many times and found ramp output/input pins and ADC read pins never share any connections ie the data read from ADC dont affect DAC ramp data in any form in program. So I like to know that suppose we drive one input pin of FPGA from one source , could it affect any output pin that connects to another load in any way , some stuff like impedance issue etc could cause such noise?

 

With Regards

Shalini

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Moderator
Moderator
6,146 Views
Registered: ‎07-23-2015

Re: FPGA pins behaviour

sha@hys What frequencies are you running your design at? What is the IO standard set for Input and Output? Which Bank is interfaced to ADC and which one to DAC?

- Giri
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Explorer
Explorer
5,877 Views
Registered: ‎05-31-2015

Re: FPGA pins behaviour

Hello,

 

Design runs at 100Mhz. The I/O standards are LVCMOS33. Bank 2 is interfaced to ADC and DAC. May I know how scenario varies with change in banks. All banks connected to VCCO 3.3V.

 

With regards

Shalini 

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