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Newbie xilinx_raju
Newbie
2,670 Views
Registered: ‎07-15-2011

Fifo generator IP core: fault in reading

I have used the Fifo generator IP core with independent read and write clock domain. I first write 100 words into the fifo and then read 100 back. But on reading i started getting data from the fourth location, not the first as should be. Is this IP core faulty or there is some other better way to use it.
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2 Replies
Teacher rcingham
Teacher
2,669 Views
Registered: ‎09-09-2010

Re: Fifo generator IP core: fault in reading

Which FPGA?
What versions of ISE and IP?
What are the clock frequencies?
Is this in simulation? If so, which simulator?
Can you post waveform diagrams?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Instructor
Instructor
2,666 Views
Registered: ‎08-14-2007

Re: Fifo generator IP core: fault in reading

If this is simulation, did you wait 100 ns for global set/reset to de-assert before starting to write

your 100 words?

-- Gabor
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