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Newbie philou66
Newbie
4,441 Views
Registered: ‎01-29-2014

Floating differential input on Spartan 6

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Hi,

I have an application with LVDS inputs on a Spartan 6 (internal termination used).

Some of the inputs may be connected or left floating. The info of "connected" or "floating" is not known by the FPGA, so I cannot put the floating pads as outputs.

What is the behavior of the diff inputs when left floating ? Randomly toggling ? Is there any kind of failsafe mechanism that keeps the IO in a defined state ? This exists in some discrete LVDS receivers like SN65LVDS179.

Regards

Philippe

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1 Solution

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Xilinx Employee
Xilinx Employee
5,823 Views
Registered: ‎07-23-2012

Re: Floating differential input on Spartan 6

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If the logical state of the differential receiver's pins is not important when they left un-driven (e.g., if input registers have been disabled), you do not need to do anything. The receiver's output might toggle if enough noise is present; however, this will not damage the device. The toggling might lead to increased power consumption and noise within the device; however, these will be fairly insignificant.

If it is necessary to keep the receiver's pins at a known logical state, the inputs can be DC-biased with a pull-up to VCCO and pull-down to GND.
The design goal is to get the input differential voltage to a level that ensure a known logic level is at the IBUFDS output while still ensuring that the signal integrity is good at the input pin.

You should select the Pull-up and Pulldown resistors such that in the undriven case the differential input voltage is greater than minimum VID for the differential input standard in the data sheet.

You should then perform an IBIS or Spice simulation with the input being driven at the desired operating frequency to ensure that the input specifications are still met and that there is good signal integrity at the input.
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Xilinx Employee
Xilinx Employee
5,824 Views
Registered: ‎07-23-2012

Re: Floating differential input on Spartan 6

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If the logical state of the differential receiver's pins is not important when they left un-driven (e.g., if input registers have been disabled), you do not need to do anything. The receiver's output might toggle if enough noise is present; however, this will not damage the device. The toggling might lead to increased power consumption and noise within the device; however, these will be fairly insignificant.

If it is necessary to keep the receiver's pins at a known logical state, the inputs can be DC-biased with a pull-up to VCCO and pull-down to GND.
The design goal is to get the input differential voltage to a level that ensure a known logic level is at the IBUFDS output while still ensuring that the signal integrity is good at the input pin.

You should select the Pull-up and Pulldown resistors such that in the undriven case the differential input voltage is greater than minimum VID for the differential input standard in the data sheet.

You should then perform an IBIS or Spice simulation with the input being driven at the desired operating frequency to ensure that the input specifications are still met and that there is good signal integrity at the input.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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Newbie philou66
Newbie
4,427 Views
Registered: ‎01-29-2014

Re: Floating differential input on Spartan 6

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Hi, thanks for your answer.

I'd like to avoid external components.I tried to set an internal pullup on the P side, and internal pulldown on the N side at the same time as the differential termination, ISE issues a warning about signal integrity.

Any experience on this ? Is this case supported by IBIS simulation ?

 

 

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Scholar austin
Scholar
4,419 Views
Registered: ‎02-27-2008

Re: Floating differential input on Spartan 6

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p,

 

One can model this in any SI simulator (add the min value resistors and see how it affects the signals).

 

Generally speaking, even a pullup or pulldown of 1K ohms will probably not affect the operation.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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