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Adventurer
Adventurer
4,739 Views
Registered: ‎11-10-2009

Galvanic isolation for LVDS I/Os (ISERDES/OSERDES xapp1064)

Hello,

 

I would like to implement a similar topology to the presented in the XAPP1064 to establish a fast point-to-point communication between two (and more) Spartan-6 devices. The problem I have is that both FPGAs are to be placed in different boards and connected with a cable (twisted pair ~3 m). For this I will need some sort of galvanic isolation.

 

The only solution I could find was the AN-1117 application note of Analog Devices, which is limited to 150 Mbps and it is quite slow for my needs. I was thinking about using magnetic isolation, as the one specified in the Ethernet standard, but a clock-forwarding form of communication will have potentially static lines (eg. data line when more 1s or 0s are transmitted together) which will make the communication impossible (this magnetic isolatin is thought for a manchester code clk-data combined line).

 

I cannot use GTPs because there will be many of these point-to-point connections, exceeding what can be found in the T series devices. A data rate to achieve per data line would be 250 Mbps.

 

Does anybody have any idea how this could be done?

 

Thank you very much in advance.

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Instructor
Instructor
4,737 Views
Registered: ‎07-21-2009

Re: Galvanic isolation for LVDS I/Os (ISERDES/OSERDES xapp1064)

Do you need to separate (isolate) grounds?  If so, then galvanic isolation (which includes simple AC coupling) is not a precise enough term.

 

Use a gig-E ethernet PHY with magnetic coupler on each end.  Simple!  An RGMII interface to the PHY is simple, compact, and well within the capabilities of Spartan-6 family devices.

 

-- Bob Elkind

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Xilinx Employee
Xilinx Employee
4,705 Views
Registered: ‎08-01-2012

Re: Galvanic isolation for LVDS I/Os (ISERDES/OSERDES xapp1064)

You can think of using LVDS with DC isolation capacitors coupling. Take care common mode voltage matching and recommending to do simulations

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Observer
Observer
2,303 Views
Registered: ‎11-26-2011

Re: Galvanic isolation for LVDS I/Os (ISERDES/OSERDES xapp1064)

I'm been trying to make a new post, but unfortunately it doesn't work. Beceause of the topic similarity I will put a question here...

 

Is it possible to assume the unused pin area between the IO banks of Spartan 6 LX150 as galvanic isolation?

Is there any posibility to configure some IO ports in order to serve as galvanic separation between specifed IO regions?

 

Best regards,

Emil

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