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Observer
6,274 Views
Registered: ‎12-08-2009

Gaussian filter implementation on a Spartan 3 DSP

Has anyone implemented a gaussian filter on a Spartan FPGA to blur an image? I am looking for design guidance on how to achieve this.

Where should I start?

Thanks

4 Replies
Explorer
6,261 Views
Registered: ‎07-27-2009

Re: Gaussian filter implementation on a Spartan 3 DSP

Yes. Have a look at the wikipedia article http://en.wikipedia.org/wiki/Gaussian_filter#Digital_implementation

• You can use a FIR style filter to approximate the response (easy, fast, well understood, good match to DSP48 resources)
• run multiple iterations of moving average (no need for multipliers if done with powers of 2 and efficient when combined with a shift register implementation+accumulator)
• transform to the frequency domain with an FFT, multiply with a Gaussian, inverse FFT (probably the most complex)

If you want to have good speed, you probably want to keep some lines of the images in FPGA memory if the main images set e.g. in DRAM.

Cheers,

Johan

Highlighted
Explorer
5,108 Views
Registered: ‎04-28-2010

Re: Gaussian filter implementation on a Spartan 3 DSP

hi,

u can use a discrete version of the gaussian filter kernel to implement ur gaussian filter.

Best Regards
Chandrajit
Tags (1)
Scholar
5,099 Views
Registered: ‎09-16-2009

Re: Gaussian filter implementation on a Spartan 3 DSP

One would assume that since you're doing this on an image, you want a 2-D Gaussian filter.

I'm pretty sure the Gaussian filter is seperable.  So if your kernel size is too large, consider

doing a seperate Y, then X filter.

Spartan 3 don't have DSP48s do they?  (Too lazy to look it up)..  You can take advantage of

the symmetry of the filter to save resources too.

Regards,

Mark

5,085 Views
Registered: ‎02-09-2012

Re: Gaussian filter implementation on a Spartan 3 DSP

usually those filters have a two axis symmetry making it possible to cut down the no of operations significantly.

one has only to make up one's mind if a parallel processing is desired or a fully sequential with only one MUL architecture + accumulator