UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer urodacus
Observer
4,454 Views
Registered: ‎04-28-2017

Generating a clock - SPI communication

Hello,

 

I'm quite new at this and I had some questions.

 

For a project, i'm linking a Spartan 6 (SPI master) to another board (SPI slave).

 

I guess I'll have to code how to manage MISO, MOSI and CS but I don't know how I'll handle the clock.

 

Should i use a quartz (oscillator) or can the FPGA "make" the clock at a desired frequency?

 

Thanks for the help,

Uro.

0 Kudos
12 Replies
Xilinx Employee
Xilinx Employee
4,433 Views
Registered: ‎09-05-2007

Re: Generating a clock - SPI communication

I have provided a PicoBlaze reference design that can access an SPI Flash device. In this case PicoBlaze generates clock pulses as and when they are required. Whether you just refer to the documentation and source code with all its comments to find out how SPI works or adopt PicoBlaze to implement the SPI Master signalling and slave protocol that you need (all in less than 30 Slices) I hope you find it a useful reference.

 

https://www.xilinx.com/products/intellectual-property/picoblaze.html

 

See 'design Files' tab and download the 'KCPSM6' package. In the zip file you will find a 'Reference Designs' folder and your initial interest will be the design in the 'SPI' folder.

 

 

Ken Chapman
Principal Engineer, Xilinx UK
0 Kudos
Scholar u4223374
Scholar
4,407 Views
Registered: ‎04-26-2015

Re: Generating a clock - SPI communication

@urodacus The FPGA can't generate clocks without a reference. Virtually any FPGA board you can find will have an oscillator already installed to provide a clock source.

 

Once you've got access to one clock, the FPGA clock management system can generate new clocks derived from that one at whatever frequency you want.

0 Kudos
Observer urodacus
Observer
4,391 Views
Registered: ‎04-28-2017

Re: Generating a clock - SPI communication


@chapman wrote:

I have provided a PicoBlaze reference design that can access an SPI Flash device. In this case PicoBlaze generates clock pulses as and when they are required.


 

Thank you for providing me this.

 

This is not for a SPI flash (though I'll need a SPI flash) but from what i understood, i can indirectly program it through FPGA with JTAG, isn't it?

 

But I may use it even though that is not a SPI flash (it's an embedded TCP/IP ethernet controller)

 

 


@u4223374 wrote:

@urodacus The FPGA can't generate clocks without a reference. Virtually any FPGA board you can find will have an oscillator already installed to provide a clock source.

 

Once you've got access to one clock, the FPGA clock management system can generate new clocks derived from that one at whatever frequency you want.


The FPGA has an internal clock, right?

 

I only used FPGA when they already were on boards (school projects, etc.). It's my first time using one without being on a board

0 Kudos
Observer urodacus
Observer
4,389 Views
Registered: ‎04-28-2017

Re: Generating a clock - SPI communication

By "without being on a board", I mean that i do the board
0 Kudos
Moderator
Moderator
4,384 Views
Registered: ‎01-15-2008

Re: Generating a clock - SPI communication

Hi Urodacus,

you can use the startup primitive to drive out the configuration clock post configuration.

https://www.xilinx.com/support/answers/33899.html

But in spartan-6 the CCLK pin is multipurpose pin, which means after configuration this pin will be user IO and startup primitive will not help here. check the above solution record explaining about this scenario for spartan devices

 

--Krishna

0 Kudos
Observer urodacus
Observer
4,381 Views
Registered: ‎04-28-2017

Re: Generating a clock - SPI communication


@kkn wrote:

Hi Urodacus,

you can use the startup primitive to drive out the configuration clock post configuration.

https://www.xilinx.com/support/answers/33899.html

But in spartan-6 the CCLK pin is multipurpose pin, which means after configuration this pin will be user IO and startup primitive will not help here. check the above solution record explaining about this scenario for spartan devices

 

--Krishna


I'm sorry but what you just said isn't clear to me.

I don't understand your reply (Startup primitive, etc.)

0 Kudos
Moderator
Moderator
4,379 Views
Registered: ‎01-15-2008

Re: Generating a clock - SPI communication

you can check the spartan-6 libraries guide for details on startup primitive(from page 314)

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/spartan6_hdl.pdf

The AR I pointed to you explains how you can use startup primitive to drive the configuration clock after configuration in CCLK pin.

configuration clock here is the internal oscillator which is used during master configuration's and this frequency is set in the bitgen settings

0 Kudos
Observer urodacus
Observer
4,377 Views
Registered: ‎04-28-2017

Re: Generating a clock - SPI communication

"This is not applicable for Spartan devices as the CCLK pin is User I/O after configuration and is not a dedicated pin."

 

That means I can't use it, right?

0 Kudos
Moderator
Moderator
4,368 Views
Registered: ‎01-15-2008

Re: Generating a clock - SPI communication

yes, you cannot drive out the configuration clock post configuration on the cclk pin in spartan-6 device by using the startup primitive.

Do you have a system clock for the fpga? i.e. how is your design clocked inside the fpga? 

0 Kudos
Observer urodacus
Observer
3,060 Views
Registered: ‎04-28-2017

Re: Generating a clock - SPI communication


@kkn wrote:

 

Do you have a system clock for the fpga? i.e. how is your design clocked inside the fpga? 


That's what I was asking in a previous post, I don't know if the FPGA has an internal clock, does he have one or do I have to use an oscillator or smth?

0 Kudos
Xilinx Employee
Xilinx Employee
3,057 Views
Registered: ‎09-05-2007

Re: Generating a clock - SPI communication

It is normal to have at least one external clock source to provide a known timing reference. However, the STARTUP_SPARTAN6 primitive has a CLKMCLK output pin that provides an internal oscillator of approximately 50MHz. This is described in UG380.

 

The PicoBlaze reference design that I suggested to you earlier is an example of an SPI Master. It shows how SPI signals can be generated and how the protocol for a device can be implemented. Yes, the reference design is for an SPI Flash devices but as a 'reference' it should be useful.

 

 

Ken Chapman
Principal Engineer, Xilinx UK
Observer urodacus
Observer
3,040 Views
Registered: ‎04-28-2017

Re: Generating a clock - SPI communication


@chapman wrote:

It is normal to have at least one external clock source to provide a known timing reference. However, the STARTUP_SPARTAN6 primitive has a CLKMCLK output pin that provides an internal oscillator of approximately 50MHz. This is described in UG380.

 

The PicoBlaze reference design that I suggested to you earlier is an example of an SPI Master. It shows how SPI signals can be generated and how the protocol for a device can be implemented. Yes, the reference design is for an SPI Flash devices but as a 'reference' it should be useful.

 

 


Yes, I didn't know that and always thought that the FPGA had an internal oscillator.

 

I'll use an external oscillator but I guess there is a maximal frequency and that sort of thing, can someone point to me where I can see that sort of things?

 

Thank you for the PicoBlaze design, I'll look it up and come back later if I have question about it !

0 Kudos