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Visitor dcm_lab
Visitor
1,797 Views
Registered: ‎07-17-2018

Generating desired clock frequency in spartan-6 FPGA in Mojo V3

I am new to FPGA and Mojo. What I am trying to do is generate a 20 MHz clock frequency from mojo and output it through an I/O pin and feed that signal to a function generator. I went through Spartan-6 documentation on clocking, but I guess that was a bit heavy. Are there any other resources online on how to do it? What is the best way to do that?

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8 Replies
1,772 Views
Registered: ‎06-21-2017

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

Let's start with two important questions.

1. What clocks are going into your FPGA?

2. What kind of signal does your function generator require?  What voltage level?  How is it terminated (50 ohms or high impedance)?

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Visitor dcm_lab
Visitor
1,747 Views
Registered: ‎07-17-2018

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

Hi,

1. The default clock is 50 MHz, but I am currently using a 150 MHz clock from FPGA for my project.

2. I need a pulse from my signal generator. I normally work around 3V -3.5V, and it is terminated by 50 Ohms impedance.

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Contributor
Contributor
1,739 Views
Registered: ‎08-09-2013

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

Hi,

By going though your initial post for generation of 20 MHz signal, use a clocking wizard IP in the Tool. Generate the 20 MHz. This signal can be send through IO.  I did not understand the second post, you need to receive a pulse?

 

Following screen shot may help you.

1.png
2.png
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Visitor dcm_lab
Visitor
1,707 Views
Registered: ‎07-17-2018

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

Hi,

Thank you for the screenshot. I need square pulses from the function generator.

 

I am using Coregen from Mojo's IDE, which I think is pretty much the same things as the one in ISE.

So, I did generate a 20 MHz clock using Coregen. Now, in my Mojo IDE, there is the core that I generated. Now, how do I ouput this signal through one of the I/O pins in my Mojo? Thank you again.

 

I have attached the .txt file for the verilog code generated by coregen.

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1,675 Views
Registered: ‎06-21-2017

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

To help, we need to know what kind of signal your function generator expects as an input, not what you want to get out of the function generator.  Does it expect a square wave clock or a sine wave reference?  What voltage range should the signal have?  Is the function generator's input terminated in 50 ohms?

 

What is the output circuit of the Mojo?  Does the FPGA drive the connector pins directly or does the signal go through another chip?  What kind of connector is on the Mojo?  Does the function generator have a BNC connector or something else?

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Visitor dcm_lab
Visitor
1,664 Views
Registered: ‎07-17-2018

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

Hi, the function generator expects a square wave pulse as an input (anywhere around 5V should be fine). And yes, I think its input is terminated at 50 ohms.

 

I am pretty sure that the FPGA drives the connector I/O pins directly and the way I am thinking about taking an output signal is to plug a 2 pin female BNC connector on the I/O pins of the mojo which is then connected to the generator by a BNC cable.

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1,659 Views
Registered: ‎06-21-2017

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

The maximum IO voltage for a Spartan 6 is 3.3V and that's if the VCCO for the bank driving the signal is powered by 3.3V.  I don't have a copy of the S6 select IO users guide handy, but I think the most a pin can source or sink is 24mA.  5 volts into 50 ohms is 100 mA.  If the function generator can run on a 3.3V input and your VCCO is 3.3V, you might be able to make this work if you gang a few (4 to 6) outputs together and set the drive strength to 24 mA.  You may exceed the simultaneously switching outputs recommendation, (or not) but it might work.

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Xilinx Employee
Xilinx Employee
1,495 Views
Registered: ‎06-30-2010

Re: Generating desired clock frequency in spartan-6 FPGA in Mojo V3

here is the link to the S6 IO UG http://www.xilinx.com/support/documentation/user_guides/ug381.pdf and data sheet http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

in the DS we give the VOH Min on page 10, for LVCMOS33 is it VCCO -0.4 so with the VCCO max being 3.45 you could get a minimum of 3.05V out, if that is too low for the function generator then a level translator maybe best.


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