09-14-2007 05:54 AM
09-17-2007 12:56 AM
09-28-2007 06:56 AM
09-28-2007 07:10 AM
Hi, Say if I have 10% of 3S700A device and target at 200 MHz, is this possible?
Maybe - it doesn't depend how full it is, just how many levels of logic you have between flipflops.
Normally I run synthesis in order to get a quite estimate on how fast the circuit can operate. Since I am using quite a lot of IP cores such as RAM, FIFO, synthesis can no longer gave such estimation. In this case do I have to perform "implement / place and route" and use the post p&r modle to simulate the system for a proper speed estimation? Is there any quicker way to do it?
That's the only way, although you don't have to run a simulation to get timing - just read the static timing analyser report.
09-28-2007 08:39 AM