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Observer zhouyun
Observer
11,267 Views
Registered: ‎09-04-2007

Hi,   I am going to start my very first FPGA design on Sp...

Hi,
 
I am going to start my very first FPGA design on Spartan 3 FPGA. I might need to clock the FPGA at over 200 MHz. Is Spartan 3 able to operate at such frequency? If yes, what speed grade should I choose?
 
Thanks in advance!
 
zy
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4 Replies
Explorer
Explorer
11,235 Views
Registered: ‎08-14-2007

Re: Hi, I am going to start my very first FPGA design on Sp...

Hi zy,

This sounds optimistic as your first design ;-)

How much logic do you need to operate at 200MHz?  If it's a small amount, then yes, it's doable, but getting a whole chipful of logic to run that quick will need extreme care in the design to keep down the logic levels between flipflops. - you can probably only afford one LUT between each FF.  According to the datasheet, the fastest you can run the DCMs is 280MHz, so bits of logic can go that fast...

Choosing a speedgrade is best done after you've got some of the design working and you can run it through the tools, to see how fast it goes.

Cheers,
Martin
Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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Observer zhouyun
Observer
11,152 Views
Registered: ‎09-04-2007

Re: Hi,   I am going to start my very first FPGA design on Sp...

Hi,
 
Say if I have 10% of 3S700A device and target at 200 MHz, is this possible?
 
Normally I run synthesis in order to get a quite estimate on how fast the circuit can operate. Since I am using quite a lot of IP cores such as RAM, FIFO, synthesis can no longer gave such estimation. In this case do I have to perform "implement / place and route" and use the post p&r modle to simulate the system for a proper speed estimation?
 
Is there any quicker way to do it?
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Explorer
Explorer
11,150 Views
Registered: ‎08-14-2007

Re: Hi, I am going to start my very first FPGA design on Sp...

Hi, Say if I have 10% of 3S700A device and target at 200 MHz, is this possible?

Maybe - it doesn't depend how full it is, just how many levels of logic you have between flipflops.

Normally I run synthesis in order to get a quite estimate on how fast the circuit can operate. Since I am using quite a lot of IP cores such as RAM, FIFO, synthesis can no longer gave such estimation. In this case do I have to perform "implement / place and route" and use the post p&r modle to simulate the system for a proper speed estimation? Is there any quicker way to do it?

That's the only way, although you don't have to run a simulation to get timing - just read the static timing analyser report.

Cheers,

Martin

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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Observer zhouyun
Observer
11,146 Views
Registered: ‎09-04-2007

Re: Hi,   I am going to start my very first FPGA design on Sp...

Hi,
 
I implement a simple multiplier. I do find some timing results, such as "setup/hold to clock" ,  "clock to pad" and "clock to setup on destination clock" . But I do not know how to interpret them.
 
I read a number of 6.029 from "clock to setup on destination clock", rise-rise. Is this mean that the minimum possible clock period is 6.029 ns?
 
 
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