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Visitor chunlin_wei
Visitor
6,917 Views
Registered: ‎12-30-2011

Higher Deserialization Factors in the doc. xapp1064

hi :

I use spartan6 device to demonstrate my design according to the reference design xapp1064, the serdes factor is 10:1. I use the Modelsim as the simulator. When I simulate my project, I find that the signal "bitslip" in the "serdes_1_to_n_clk_pll_s10_diff" can not stop if I set the pattern 10'b1111100000. And the receive side can not receive the right data because of this. So can you help me to understand why?

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11 Replies
Instructor
Instructor
6,911 Views
Registered: ‎07-21-2009

Re: Higher Deserialization Factors in the doc. xapp1064

You understand that the maximum serdes factor is 8:1 in Spartan-6 devices, correct?

For 10:1 overall factor, you must use 5:1 in the ISERDES2 block, and perform another 2:1 deserialisation in the fabric logic.  In this case, you cannot use DDR mode, only SDR mode in the ISERDES2 blocks.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Visitor chunlin_wei
Visitor
6,893 Views
Registered: ‎12-30-2011

Re: Higher Deserialization Factors in the doc. xapp1064

there are three modes in the reference desing, one is SDR, DDR and the last is using the PLL which is a little different from the SDR because of the frenquency of the synchronous clock.
yes, you are right for the 10:1, but my question is why the "bitlip" signal can not stop in the "10:1"reference design.
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Instructor
Instructor
6,889 Views
Registered: ‎07-21-2009

Re: Higher Deserialization Factors in the doc. xapp1064

but my question is why the "bitlip" signal can not stop in the "10:1"reference design.

 

I do not understand your question, but I can affirm that BITSLIP does indeed work.  It is not well documented, but it *does* work.  And BITSLIP does not care what the deserialisation ratio is.  Again, the limit of the Spartan-6 ISERDES block is 8:1.  A 10:1 problem will need to be implemented as 5:1 (SDR only) in the ISERDES block.

 

If  you have a specific question or problem with BITSLIP, you should describe the problem... providing all reasonable and useful detail, including your code.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor chunlin_wei
Visitor
6,868 Views
Registered: ‎12-30-2011

Re: Higher Deserialization Factors in the doc. xapp1064

thank you for your answer. I know the limit of the Spartan-6 ISERDES block is 8:1. About the high deserialization factors, there is a reference design in the doc.xapp1064. When I use the reference deisgn, I find some problems in it, and it makes the bitslip signal can not stop in the reference deisgn. so my question is that do we need to change something about the reference design?
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Advisor joelby
Advisor
6,867 Views
Registered: ‎10-05-2010

Re: Higher Deserialization Factors in the doc. xapp1064

Can you please explain exactly what you mean by "bitslip signal can not stop"? Ideally, provide a diagram or ISim screenshot.

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Visitor chunlin_wei
Visitor
6,861 Views
Registered: ‎12-30-2011

Re: Higher Deserialization Factors in the doc. xapp1064

The bitslip signal will not generate a pulse until it find the data that is the same as you set in the serial data current. But in the reference design, the bitslip signal generates a pulse every five clock because it not find the same data as "pattern" which I set in the design.
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Instructor
Instructor
6,859 Views
Registered: ‎07-21-2009

Re: Higher Deserialization Factors in the doc. xapp1064

The bitslip signal will not generate a pulse until it find the data that is the same as you set in the serial data current. But in the reference design, the bitslip signal generates a pulse every five clock because it not find the same data as "pattern" which I set in the design.

 

What you describe is not a problem with the BITSLIP function in the ISERDES2 block.  There are two possibilities:

 

  • The data output from the ISERDES2 block is incorrect (a configuration bug in the input logic, or the data being received is being transmitted incorrectly, for example).
  • The word framing logic which generates BITSLIP commands is incorrect

There are many ways the word framing logic can be incorrect.  The logic which generates (or does not generate) the BITSLIP command is your implementation to design and simulate and debug.  The complication of 2:1 deserialisation in the fabric logic complicates your word framing logic design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor chunlin_wei
Visitor
6,856 Views
Registered: ‎12-30-2011

Re: Higher Deserialization Factors in the doc. xapp1064

The word framing logic which generates BITSLIP commands is from the reference design. And the BITSLIP in the reference design is function as a signal to make your local clock that generate according to the sync clock to have the phase with the sending serial data clock.
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Instructor
Instructor
6,854 Views
Registered: ‎07-21-2009

Re: Higher Deserialization Factors in the doc. xapp1064

The word framing logic which generates BITSLIP commands is from the reference design. And the BITSLIP in the reference design is function as a signal to make your local clock that generate according to the sync clock to have the phase with the sending serial data clock.

 

I suggest you modify the BITSLIP command generator logic design so that it functions correctly for your application.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor neustr
Visitor
2,821 Views
Registered: ‎02-16-2012

Re: Higher Deserialization Factors in the doc. xapp1064

I want use spartan 6 device as a data concentrator for several TI ADCs - ADS5282 (each  ADC has 8 serial (LVDS, DDR,12bit) chann + clk + frame, 65MSPS). As I understand xapp1064 I have to use DDR mode and 6:1 factor first and then use additional 2:1 deser in fpga logic...  It's not clear how I can use frame (1 for 8 data chann) for alignment?

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Instructor
Instructor
2,814 Views
Registered: ‎07-21-2009

please start a new thread

neustr,

 

This is a complicated subject which is unrelated to this thread.  Please start a new thread in the Spartan Family FPGAs forum.

 

It is considered both rude and confusing to add an unrelated problem or topic to an existing thread.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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