05-16-2011 01:49 AM
1 to 12 deseialization with an input CLK of 500MHz i tried to use
but i does not produce the output clocks from th eserdes_1_to_n_clk_pll_s16_diff component, when i imput a 500mhx clock on clkin_p & clkin_n lines i get nothing out
My ADC has a 12bit serial output hand has 8 LVDS output channels each outputing 12bit serial data @500MHz I amd using the serdes modies in SDR mode and BS false
I will also need to to change the data rate to 640Mhz/750Mhz & 1Ghz
there is very little inform,ation about how to drive these modules
05-16-2011 08:08 AM - edited 05-16-2011 08:35 AM
I assume you are using Spartan-6 (you don't specify).
Have you read through the ISERDES2 section of UG381?
Have you checked out XAPP1064? Are you using design files from this XAPP?
There is much information in these.
Is this a custom board design, or are you using a development board?
If you have specific questions or problems, it helps if you describe them with as much detail as possible.
1GHz serial input data rate is getting very close to the datasheet maximum.
Have you tried running your design at much lower serial bitrates, until you get your design logic debugged?
-- Bob Elkind
05-16-2011 09:08 AM
I have looked the the app note you suggested indeed this is were i got my orignal source code from.
It is a custom desgin with a spartan 6, I will be using a Hittite ADC HMCAD1520 in singal channel 12 bit mode. The ADC will be sampling at 640MSPS outputing on 8 LDVS lines (16 physical lines) in 12 bit mode.
The data will be clocked in @960Mhz
(640/8)*12 = 960Mhz
I have never used SERDES above 1 to 6. For this application i will need 1 to 12, the code i attached was just to try tro get the module to simulate, but the CLK_PLL module deos not pass the desired CLKs to the s16 module. CLearly i have missed interpreted how the modules work can someone enlighten me?
05-16-2011 09:35 AM
The Hittite ADC is an interesting device. Are you designing this board for Hittite?
Drive ADC input from the FPGA, so you can control the input of the ADC from sample to sample, and you can (indirectly) control the data output of the ADC.
Lower the ADC input clock frequency, thereby lowering the serial data frequency. Debug function first, then tweak for bandwidth.
Try driving the ADC input LOW for 8 samples, then drive the input HIGH for 8 sample. This should give you a consistent pattern of serial data on the ADC outputs, and should also give you an easily recognisable pattern at the output of your ISERDES2 blocks (if connected and operating correctly).
You took a risk by assigning your IO pins on the board before you had your FPGA design completed enough to successfully place and route.
I hope this helps you...
-- Bob Elkind
12-06-2011 06:29 AM
I'm working also with a Hittite ADC HMCAD1511 device. Does anybody have an example implementation?
Thank you for your ideas
12-06-2011 11:39 AM
>>> when i imput a 500mhx clock on clkin_p & clkin_n lines i get nothing out
Check the clock paths...
I had the same thing - the output of the serdes was always low, altough the FABRICOUT was OK.
The problem was one extra BUFG in the high speed clock path ( PLL -> BUFG ->BUFPLL -> serdes.)...
There were no errors or warnings, so it is really hard to catch such a bug.
03-17-2012 01:38 PM
03-22-2012 03:34 AM - edited 03-22-2012 03:40 AM
>The problem was one extra BUFG in the high speed clock path ( PLL -> BUFG ->BUFPLL -> serdes.)...
>There were no errors or warnings, so it is really hard to catch such a bug.
I had similar problems when designing an interface für also around 500 MHz with SERDES exceeding the limitations of a SERDES IO. I had to catch 7 / 8 bits per channel and synchronize the SERDES clock to an external clock and of 60...90 MHz. I finally came out with a 4+3 / 4+4 structure using master slave. I had to instantiate all manually since Coregen gave me someting which caused an error at the synthesis / mapping phase as I remember correctly.
There was allway an extra buffer automatically inserted by the core which intersected with the buffers to be used for the SERDES configuration according to Xilinx APPS and recommendation of the FAE. It was not possible to force COREGEN to leave the buffer away.
I will be in the situation to port that design to S6 in the near future possibly and will follow this tread.
07-12-2016 03:17 AM
We have just started to work with Hittite HMCAD 1511. I have been looking around for the code they use for the eval board. We have some problems with communicating with the chip through the SPI and suspect that the start-up sequence described in the docs is not completely right.
I will appreciate a lot if you could asend me a link to the source code Hittite is using. This will surely speed up things.
Many thanks in advance
07-12-2016 07:35 AM - edited 07-12-2016 07:35 AM
@Pawel Kopyt: This forum thread started in 05-16-2011. It is very old. Please create a separate thread. If your query related to this old thread then simply refer forum link in your new forum thread. Thanks for understanding