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Visitor corium
Visitor
12,018 Views
Registered: ‎07-28-2011

How do I know if DIFF_TERM is set to be TRUE correctly?

I am using Spartan 6 and will need to activate the internal 100 ohm terminator for a pair of clock inputs. According to the "Spartan 6 SelectIO Resources User Guide" and some previous discussions in the forum, the DIFF_TERM attribute of the corresponding ports shall be set to be true in the constraint file and an IBUFDS shall be used in the main file in order to turn on the internal terminator.

Therefore, I declare and instantiate the IBUFDS as below:

component IBUFDS
generic (DIFF_TERM : BOOLEAN;
 IBUF_LOW_PWR : BOOLEAN;
 IOSTANDARD : string );
port (     I  : in    std_logic;
              IB : in    std_logic;
             O  : out   std_logic);
end component;

IBUFDS     
generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE, IOSTANDARD => "DEFAULT")      
port map ( I=>DCLK_P           ,IB=>DCLK_N             ,O=>dco_in );

Then in the constraint file, the attributes were set as:

NET "DCLK_N" IOSTANDARD = LVDS_33;  
NET "DCLK_P" IOSTANDARD = LVDS_33;

NET "DCLK_N" DIFF_TERM = "TRUE";
NET "DCLK_P" DIFF_TERM = "TRUE";

Could someone check are these right or not?

My problem is that the external DCLK signal looks like a triangle wave with an oscilloscope, no matter the DIFF_TERM is set to TRUE or FALSE. Then in ChipScope, the DCLK signal jitters very significantly and does not look like a good clock signal at all.

I know it may not be due to the differential terminator setting but just in case I didn't set the DIFF_TERM correctly, I hope someone may help to have a look. Thanks! 

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13 Replies
Teacher eteam00
Teacher
12,014 Views
Registered: ‎07-21-2009

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

Both the FPGA editor and PlanAhead will show the termination attributes of the IOs.

[note:  see Jim Wu's post #12 in this thread below]

 

I'm not sure that there is a simpler method of verification.  The post place/route design summary files do NOT reflect all output termination selections.  PULLUP and PULLDOWN is shown, but OUT_TERM attributes, for example, are not included in the reports.

 

I've submitted a webcase on this missing information, and some future tools update will likely fill in this gap in the reports.  In the meantime, FPGA Editor and PlanAhead (I've used FPGA Editor, to confirm).

 

In FPGA Editor, select the IOB, display PROPERTIES, and select the Configuration tab inside the Properties box.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Scholar austin
Scholar
12,011 Views
Registered: ‎02-27-2008

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

c,

 

If the signal looks like a tirangle wave, it is not the termination.


That is either the 'scope is just too slow to actually see the square wave, or the square wave has been heavily loaded down and is no longer square from capacitance, cables, or just poor signal integrity (wrong impedance of board traces/cables).

 

This could also be because the source has too high an output impedance (not LVDS standard).

 

Nice crisp and sharp edges should be visible.  Without termination, I would expect overshoot & undershoot (above and below the expected or nominal voltages for LVDS), and perhaps some ringing from the reflections.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Teacher eteam00
Teacher
12,009 Views
Registered: ‎07-21-2009

Verify the measurement setup

If the signal looks like a triangle wave, it is not the termination.

 

Agreed.


That is either the 'scope is just too slow to actually see the square wave, or the square wave has been heavily loaded down and is no longer square from capacitance, cables, or just poor signal integrity (wrong impedance of board traces/cables).

 

On at least one occasion in these forums, incorrect scope setup resulted in similar waveform display which was misleading.

 

  • What is the clock frequency?
  • What is the scope (and probe) bandwidth?
  • Is your scope probe properly GNDed?
  • Have you used the same scope/probe setup to display other signals, and seen good, clean edges?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Advisor evgenis1
Advisor
12,002 Views
Registered: ‎12-03-2007

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

Hi,

 

One way to know if your constraints took effect is to check PAD report. Attached is an example screenshot with DIFF_TERM in the signal integrity column. Another way is to look for warnings in the Translate (ngdbuild) report.

 

 

Thanks,

Evgeni

Tags (1)
diff_term.jpg
Teacher eteam00
Teacher
12,000 Views
Registered: ‎07-21-2009

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

Evgeni,

 

The "OUT_TERM = UNTUNED_25" attribute is confirmed in FPGA editor.

The "OUT_TERM = UNTUNED_25" attribute does not appear in the ISE GUI Pinout Report.

The "OUT_TERM = UNTUNED_25" attribute does not appear in the xxxx.pad output file.

The "OUT_TERM = UNTUNED_25" attribute does not appear in ADEPT reports. UPDATED:  see Jim Wu's post #12 in this thread below

 

And yes, both the 'Signal Integrity' and 'Termination' output options are selected.

 

I believe this is a bug or oversight which affects Spartan-6 designs (the original context of this thread), but not Virtex-n designs.  Please correct me if you think I'm mistaken.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor corium
Visitor
11,989 Views
Registered: ‎07-28-2011

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

Hi eteam00, from the FPGA editor, the pair of differential ports are not the same. In the P pins the DIFF_TERM is true but in the N pin there is no such information.Please have a look:

 

FPGA_Editor.JPG

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Visitor corium
Visitor
11,988 Views
Registered: ‎07-28-2011

Re: Verify the measurement setup

The clock frequency is 60 MHz.
The probe bandwidth is 100 MHz.
I think the probe shall be properly GNDed as when I use it to see other digital signals they look all right, with good clean edges.

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Visitor corium
Visitor
11,987 Views
Registered: ‎07-28-2011

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

As suggested by evgenis1, I also check the Pinout Report from the ISE. It looks like the DIFF_TERM for both pins are set all right. While as shown previously, in the FPGA editor the N pin has no DIFF_TERM information. Does it imply that they are not set correctly?

 

 

PAD_report.JPG

 

I agree that the triangle shape of the signal is not due to the termination. But I doubt that the internal terminator is set correctly, because: I have another pair of this differential signal coming from another chip (same model) with identical settings. I hand soldered an 100 ohm resistor across the input ports to the FPGA, and set the DIFF_TERM=FALSE. When i look at it with the oscilloscope, the swing of this signal is about 50% smaller than the one below, which has no external resistor. If the DIFF_TERM has been set correctly, I shall see triangle waves of similar amplitude/swing from both of them right?

 

So, what went wrong with my VHDL codes? or are there other attributes I shall pay attention to? Say the PULLUP/PULLDOWN? or the power suplly to the LVDS bank? Could you please comment on it?

 

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Teacher eteam00
Teacher
11,983 Views
Registered: ‎07-21-2009

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

You have at least two questions worth pursuing:

 

1.  Is the DIFF_TERM attribute being applied correctly?

2.  Is the DIFF_TERM internal termination useful?

 

These are two diferent questions.  Xilinx does not represent the DIFF_TERM to be 100-ohm +/- 1%.  You must inspect the IBIS models for understanding the tolerance of variation of the internal termination settings.

 

You have compared a diff pair without DIFF_TERM to a diff pair with external 100-ohm termination.

Have you compared a diff pair without DIFF_TERM to a diff pair with DIFF_TERM for differences?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Highlighted
Advisor evgenis1
Advisor
6,227 Views
Registered: ‎12-03-2007

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

Hi,

 

FPGA Editor doesn't show DIFF_TERM on N pin, only on P. One explanation is that pad and IDDR primitive for P are shown in one IOB site, and corresponding N pin is connected to that P IOB. DIFF_TERM is between N and P. So if you see DIFF_TERM on P, it's ok - that's how FPGA Editor displays it.

 

 

Thanks,

Evgeni 

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Xilinx Employee
Xilinx Employee
6,213 Views
Registered: ‎11-28-2007

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

A few things:

 

  • The ISE GUI Pinout report and the .pad output file are the same thing. They report UNTUNED_nn attributes for some signals, but not all of them, which I guess is worst than not report anything at all.
  • FPGA editor can confirm these attributes in the NCD. However, currently (as of 13.2) PlanAhead can NOT. It displayes the attributes from the netlist and UCF, NOT from the NCD.
  • Bob, per your request, ADEPT v0.44.2 now displays DIFF_TERM, IN_TERM, and OUT_TERM for Spartan6 designs. Their values can be from UCF or NCD. Check enhancements to Spartan6 Pin Table View for more details.

@eteam00 wrote:

Evgeni,

 

The "OUT_TERM = UNTUNED_25" attribute is confirmed in FPGA editor.

The "OUT_TERM = UNTUNED_25" attribute does not appear in the ISE GUI Pinout Report.

The "OUT_TERM = UNTUNED_25" attribute does not appear in the xxxx.pad output file.

The "OUT_TERM = UNTUNED_25" attribute does not appear in ADEPT reports.

 

And yes, both the 'Signal Integrity' and 'Termination' output options are selected.

 

I believe this is a bug or oversight which affects Spartan-6 designs (the original context of this thread), but not Virtex-n designs.  Please correct me if you think I'm mistaken.

 

-- Bob Elkind




Cheers,
Jim
Teacher eteam00
Teacher
6,205 Views
Registered: ‎07-21-2009

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

  • The ISE GUI Pinout report and the .pad output file are the same thing. They report UNTUNED_nn attributes for some signals, but not all of them, which I guess is worst than not report anything at all.

First I've heard of this -- good to know.

 

  • FPGA editor can confirm these attributes in the NCD. However, currently (as of 13.2) PlanAhead can NOT. It displays the attributes from the netlist and UCF, NOT from the NCD.

Another good 'heads up'.

 

  • Bob, per your request, ADEPT v0.44.2 now displays DIFF_TERM, IN_TERM, and OUT_TERM for Spartan6 designs. Their values can be from UCF or NCD. Check enhancements to Spartan6 Pin Table View for more details.

Thanks, Jim, this is a help.  It should also be useful to Evgeni.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor corium
Visitor
6,196 Views
Registered: ‎07-28-2011

Re: How do I know if DIFF_TERM is set to be TRUE correctly?

Thank you for the suggestion. However, I have reconfigured the FPGA again today and it seems that the 100 ohm terminator has been applied properly. What I can see now is:


1. With DIFF_TERM on or off, from the same differential pair, the voltage swing is smaller or larger;

2. When comparing two differential pair, one with external 100 ohm terminator, and the other with DIFF_TERM set to TRUE, the waveform looks similar, in terms of both shape and swing.


But I honestly am only using the same codes that I pasted before. The only difference is that I previously keep reconfiguring the FPGA with ChipScope. But this time I closed ChipScope, configure the FPGA, then use ChipScope to observe the signals.

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