cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Anonymous
Not applicable
7,744 Views

How to create Slave Serial file for more than one Spartan 6 FPGA?

Jump to solution

We have a XC6SLX25 currently being properly programmed from a host computer using a *.bit file. We are trying to add a XC6SLX4 to the serial chain. We believe we have implemented the hardware and selected the correct drive options for the done bit for this 2nd device. We believe we have read the Spartan 6 configuration guide (DS160) carefully as well as many other application notes (xapp951.pdf, UG332, xapp058, and many more).

 

We believe we do not know how to build the configuration file for the 2 devices in series. We have tried concatenating various files in various ways by hand (an app note says this won't work). We have tried programming using a MCS file as if we were programming from a Platform Flash device that contains both programs.

 

We have a working system when we do not extend the serial chain and program the 2nd device via JTAG.

 

Thank you in advance.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Anonymous
Not applicable
10,069 Views

We are now able to program our FPGAs in Slave Serial mode. Thank you for all your help. This is what I received from our programmer:

 

I was able to successfully program both FPGAs, monitor the clock generated by the ADC FPGA, and run a data capture which collected ~600 MB of raw data.  Skipping all of the intermediate steps, here is what worked:

 

1. Slowed the programming clock speed by a factor of 16.  (I haven't tried any settings between 1 and 16.)

2. Started with the combo_LittleFirst.mcs file generated by Mike Yee on 8/9 and replaced the second start code and the commands immediately following it with 0xFFs.

 

This solution still requires modification to the file generated mcs file, but it is something that we could program into software if required.

View solution in original post

0 Kudos
8 Replies
Highlighted
Instructor
Instructor
7,743 Views
Registered: ‎07-21-2009

The problem might be

  • The configuration file(s) you generate
  • The board design
  • The processor which is serving the configuration bit to the FPGAs.

To troubleshoot this problem, the following would be helpful:

  • Board schematics for the FPGAs and the processor which is serving configuration data to the FPGAs.
  • Description of the levels and sequences of CCLK, INIT_B (FPGA0), INIT_B (FPGA1), DONE (FPGA0), DONE (FPGA1).

You did not specify the configuration mode for the first FPGA in the chain, so should we assume that both are set up for SLAVE SERIAL configuration mode?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Professor
Professor
7,734 Views
Registered: ‎08-14-2007

In my experience, the most common problem with using an embedded processor to supply

a bitstream is getting the bit order wrong.  The .bit files and any .mcs file prepared for SPI

flash should be shifted out MSB first.  If you prepare a file for a Xilinx serial PROM, I believe that

the bit order is reversed, so the LSB should be shifted first.  You can tell from the start of

the hex data in the .mcs file.  After some number of FF bytes, you should see the startup

string:

 

AA 99 55 66

 

If the bits have been swapped, you'll instead see:

 

55 99 AA 66

 

which would mean you need to shift the data LSB first.

 

If you don't want the hassle of decoding the .mcs format, you can generate a simple hex

file using Impact.  This file has only the ASCII hex data without any addressing or other

formatting, and can therefore easily be used by an embedded processor, or converted

back to straight binary to save space in your embedded system.  By default, Impact swaps

bits when creating the .hex file.

 

-- Gabor

-- Gabor
0 Kudos
Highlighted
Anonymous
Not applicable
7,728 Views

Thank you very much for your prompt replies. Our initial setup is with the SLX25 being programmed in slave serial configuration. This programming is very robust with the single device programmed from a *.bit file. 

 

As we extend the slave serial connections to include a SLX4 FPGA, realize that there are many application notes to describe the hardware, but we cannot find information on how to create the slave serial file for multiple devices. We have read that it is not a simple concatenation of 2 bit or mcs files. Is there a tool that does this concatenation?

 

I am not certain that we can program our first device from a single *.mcs file, I will verify this. We may indeed have something bit swapped.

 

I have attached partial schematics of the 2 FPGAs and configuration connections.

 

Thank you again,

Mike

0 Kudos
Highlighted
Professor
Professor
7,726 Views
Registered: ‎08-14-2007

Impact allows you to "prepare a PROM file" for multiple devices in a chain.  The output

of this is a single .mcs (or other format depending on selections) file that has both bitstreams

embedded in it.  The trick is to start to prepare a PROM file "for a single FPGA" (misleading)

and when you get to the part of adding .bit files, add all of the FPGA devices in your chain

one after another.  After you add the first bitstream file you'll get a pop-up dialogue like:

 

 

Just click "yes" and continue to add as many .bit files as there are FPGA's in the chain.

 

-- Gabor

-- Gabor
0 Kudos
Highlighted
Instructor
Instructor
7,720 Views
Registered: ‎07-21-2009

The schematic page labeled "SLX25_Side.pdf" shows 1K pulldown Rs on M1, M0 pins.  Suggest you try pullup resistors instead (for slave serial configuration mode).  I believe you can use iMPACT "device check" to verify that the M0 and M1 pins are 'sensed' correctly by the FPGA.

 

It would help to have a design description to accompany the 3 schematic pages.  How does your board configure the FPGAs (or how is your board supposed to configure the FPGAs)?

 

From previous post in this thread:

 

To troubleshoot this problem, the following would be helpful:

  • Board schematics for the FPGAs and the processor which is serving configuration data to the FPGAs.
  • Description of the levels and sequences of CCLK, INIT_B (FPGA0), INIT_B (FPGA1), DONE (FPGA0), DONE (FPGA1).

To this I would add:  Description of levels and sequences of DIN to the second FPGA (pin U21.7).

 

You have an XCF08 on the board.  Does configuration from this memory work correctly?

Finally. board layout (signal integrity) may be contributing to your problems (or perhaps not).  Scope waveforms of the CCLK and DIN signals might provide useful clues, if the probe points are near the FPGA pins.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Highlighted
Anonymous
Not applicable
7,712 Views
Thank you very much for your replies!!! I am sorry for not sending complete schematics. Due to IP concerns, we agreed not to distribute the schematic where the SLX25 is used, and I did not show the dip switches that pull up M[0-3]. We have been using "generate a prom file" to create our programming file. I am glad we are constructing the programming file in a good way. Our embedded programmer says that we are getting data on DOUT of the first device, but it seems abbreviated. He says there is a "header" that occurs 3 times, once at the beginning, twice more in the middle. He believes that this header allows an FPGA to pass data through. He believes this header should only occur once after the beginning (total of 2). He is experimenting with removing one instance and the data associated with it. Thank you, Mike
0 Kudos
Highlighted
Anonymous
Not applicable
10,070 Views

We are now able to program our FPGAs in Slave Serial mode. Thank you for all your help. This is what I received from our programmer:

 

I was able to successfully program both FPGAs, monitor the clock generated by the ADC FPGA, and run a data capture which collected ~600 MB of raw data.  Skipping all of the intermediate steps, here is what worked:

 

1. Slowed the programming clock speed by a factor of 16.  (I haven't tried any settings between 1 and 16.)

2. Started with the combo_LittleFirst.mcs file generated by Mike Yee on 8/9 and replaced the second start code and the commands immediately following it with 0xFFs.

 

This solution still requires modification to the file generated mcs file, but it is something that we could program into software if required.

View solution in original post

0 Kudos
Highlighted
Professor
Professor
7,674 Views
Registered: ‎08-14-2007

This solution still requires modification to the file generated mcs file, but it is something that we could program into software if required.

 

The PROM file generator does this for you when you add more than one .bit file to the PROM.  You can

run the PROM file generator from a batch file (promgen.exe) if you want to make a build script.

 

-- Gabor

-- Gabor
0 Kudos