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22,633 Views
Registered: ‎08-31-2010

How to declare two bit input in UCF of verilog

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This is my code


module alu2bit(aluout,result,zero,one,two,three,four,five ,six,seven,eight,nine,a,b,select); 
output [3:0] aluout,result; // the result
output [3:0] zero,one,two,three,four,five,six,seven,eight,nine;
input [1:0] a,b; // input a and b 
input [1:0] select;
reg [3:0] aluout,result;
reg [3:0] zero,one,two,three,four,five,six,seven,eight,nine;

always@(a or b)
begin
case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase
if (aluout==4'd0) result=zero;
else if (aluout==4'd1) result=one;
else if (aluout==4'd2) result=two;
else if (aluout==4'd3) result=three;
else if (aluout==4'd4) result=four;
else if (aluout==4'd5) result=five;
else if (aluout==4'd6) result=six;
else if (aluout==4'd7) result=seven;
else if (aluout==4'd result=eight;
else if (aluout==4'd9) result=nine;
else result=zero; 
end
endmodule


I want my LEDs to glow as per my result. how can i tell UCF about my two bit input data a and b

U can also give comments to refine my code

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1 Solution

Accepted Solutions
Moderator
Moderator
18,246 Views
Registered: ‎07-30-2007

Re: How to declare two bit input in UCF of verilog

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You forgot the reg.  This works for me.  You will have to assign the one two three etc to the pin in the ucf. 

 

 

module alu2bit(aluout,result,zero,one,two,three,four,five ,six,seven,eight,nine,a,b,select);
output [3:0] aluout,result; // the result
output reg zero;
output reg one;
output reg two;
output reg three;
output reg four;
output reg five;
output reg six;
output reg seven;
output reg eight;
output reg nine;
input [1:0] a,b; // input a and b
input [1:0] select;
reg [3:0] aluout,result;

always@(*)
begin
case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase
zero <= (aluout==4'd0) ? 1'b1:1'b0;
one <= (aluout==4'd1) ? 1'b1:1'b0;
two  <= (aluout==4'd2) ? 1'b1:1'b0;
three <= (aluout==4'd3) ? 1'b1:1'b0;
four <= (aluout==4'd4) ? 1'b1:1'b0;
five <= (aluout==4'd5) ? 1'b1:1'b0;
six  <= (aluout==4'd6) ? 1'b1:1'b0;
seven <= (aluout==4'd7) ? 1'b1:1'b0;
eight <= (aluout==4'd8) ? 1'b1:1'b0;
end
endmodule

 

 

 

 

-R

 




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26 Replies
Mentor awillen
Mentor
22,624 Views
Registered: ‎11-29-2007

Re: How to declare two bit input in UCF of verilog

Jump to solution

From your other posts I can see that you already know how to write constraints for you in- and output signals. If you have a vector, like a, then you can address the individual bits like this:

NET "a<0>" LOC=...

 

As for your code:

  • consider using a case statement instead of nested if-then-else
  • use always @(*) instead of always @(a or b), except if you have very good reasons (which you don't, in this case) – especially since you forgot a signal here (select)

 

Adrian



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
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22,619 Views
Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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I am unable to make my bit file it is giving error message.

 

ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(1]: NET
"eight" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file. 

This error is from one to eight.

 

My Code is 

 

 

module alu2bit(aluout,result,a,b,select); 
output [3:0] aluout;        // the result
output [3:0]result;
input [1:0] a,b;         // input a and b 
input [1:0] select;
reg [3:0] aluout,result;
reg [3:0] zero,one,two,three,four,five,six,seven,eight,nine;
always@(a or b)
begin
case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase
if (aluout==4'd0) result=zero; // no LED will glow
else if (aluout==4'd1) result=one;
else if (aluout==4'd2) result=two;
else if (aluout==4'd3) result=three;
else if (aluout==4'd4) result=four;
else if (aluout==4'd5) result=five;
else if (aluout==4'd6) result=six;
else if (aluout==4'd7) result=seven;
else if (aluout==4'd8) result=eight;
else if (aluout==4'd9) result=nine;
else result=zero; 
end
endmodule
My UCF is
NET "a<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; //for a input
NET "a<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; //for a input
NET "b<0>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; // for b input
NET "b<1>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; // for b input
NET "select<0>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; //for a input
NET "select<1>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; //for a input
NET "one" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "two" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "three" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "four" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "five" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "six" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "seven" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "eight" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
Plz help me.
I want my eight LEDs to glow with eight different math operation result



 

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Teacher eteam00
Teacher
22,615 Views
Registered: ‎07-21-2009

Re: How to declare two bit input in UCF of verilog

Jump to solution

Is "eight" the name of a pin, or the name of a 4-bit variable?

 

Is "eight" an input or an output?  If it's an output, where is a value assigned to "eight"?

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Highlighted
22,610 Views
Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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The problem is not with eight only,it is from one to eight.

 

 

ERROR:ConstraintSystem:59 - Constraint <NET "one" LOC = "F12" |>
   [alu2bit.ucf(11)]: NET "one" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(11)]:
   NET "one" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(11)]: NET
   "one" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(11)]: NET
   "one" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "two" LOC = "E12" |>
   [alu2bit.ucf(12)]: NET "two" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(12)]:
   NET "two" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(12)]: NET
   "two" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(12)]: NET
   "two" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "three" LOC = "E11" |>
   [alu2bit.ucf(13)]: NET "three" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(13)]:
   NET "three" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(13)]: NET
   "three" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(13)]: NET
   "three" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "four" LOC = "F11" |>
   [alu2bit.ucf(14)]: NET "four" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(14)]:
   NET "four" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(14)]: NET
   "four" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(14)]: NET
   "four" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "five" LOC = "C11" |>
   [alu2bit.ucf(15)]: NET "five" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(15)]:
   NET "five" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(15)]: NET
   "five" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(15)]: NET
   "five" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "six" LOC = "D11" |>
   [alu2bit.ucf(16)]: NET "six" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(16)]:
   NET "six" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(16)]: NET
   "six" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(16)]: NET
   "six" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "seven" LOC = "E9" |>
   [alu2bit.ucf(17)]: NET "seven" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(17)]:
   NET "seven" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(17)]: NET
   "seven" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(17)]: NET
   "seven" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "eight" LOC = "F9" |>
   [alu2bit.ucf(18)]: NET "eight" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVTTL |> [alu2bit.ucf(18)]:
   NET "eight" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <SLEW = SLOW |> [alu2bit.ucf(18)]: NET
   "eight" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <DRIVE = 8 ;> [alu2bit.ucf(18)]: NET
   "eight" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
I just want to tell the kit that if result is one, LED1 should glow
if the result of ALU is 2, then LED 2 should glow.
Something is wrong in my code.
I am using one two ...... till eight just to tell the kit

 

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Teacher eteam00
Teacher
22,606 Views
Registered: ‎07-21-2009

Re: How to declare two bit input in UCF of verilog

Jump to solution

You didn't answer my questions.

Answer the questions for "eight" and you will also have the answers for zero through seven.

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
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4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
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22,602 Views
Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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I have declared one to eight as 4 bit variable

They are neither input ,nor output 

they are just registers.

I also tried to declare themas registers but problem still exists

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Teacher eteam00
Teacher
22,599 Views
Registered: ‎07-21-2009

Re: How to declare two bit input in UCF of verilog

Jump to solution

I have declared one to eight as 4 bit variable

Where are these variables assigned a value?

They are neither input ,nor output

Is there an entry for "eight" in your .UCF file?  If so, what does that entry mean?

-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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22,594 Views
Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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Actually what i want is that if result is one then LED F12 should glow and so on.

plz tell me solution i m tired now to resolve the issue

 

 

NET "one" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "two" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "three" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "four" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "five" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "six" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "seven" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "eight" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

 

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Teacher eteam00
Teacher
22,591 Views
Registered: ‎07-21-2009

Re: How to declare two bit input in UCF of verilog

Jump to solution

I'm tired also.  Get some sleep, we'll pick it up when you're back and ready for action.

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
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Registered: ‎02-25-2008

Re: How to declare two bit input in UCF of verilog

Jump to solution

 


@moonnightingale wrote:

Actually what i want is that if result is one then LED F12 should glow and so on.

plz tell me solution i m tired now to resolve the issue

 

 


The solution is to get a job outside of the electronics field.

 

----------------------------Yes, I do this for a living.
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Mentor awillen
Mentor
10,115 Views
Registered: ‎11-29-2007

Re: How to declare two bit input in UCF of verilog

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For f**k's sake, read what Bob said! Do you think he's writing just to get his post count up?


I have declared one to eight as 4 bit variable

Where are these variables assigned a value?

They are neither input ,nor output

Is there an entry for "eight" in your .UCF file?  If so, what does that entry mean?

 


 

Those questions are crucial to your problem. Think about them. Try to answer them. If you can't answer them, then say so, but don't just skip over them.



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
Teacher eteam00
Teacher
10,108 Views
Registered: ‎07-21-2009

Re: How to declare two bit input in UCF of verilog

Jump to solution

Do you think he's writing just to get his post count up?

You mean I'm not?

 

The fellow has been working hard on this all weekend long, and he's frazzled.  That can be fixed.

 

- Bob

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Moderator
Moderator
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Registered: ‎07-30-2007

Re: How to declare two bit input in UCF of verilog

Jump to solution

 

I think this is what you're looking for:

...

output reg  zero,one,two,three,four,five,six,seven,eight,nine;

....

set zero to eight to zero in the beginning of your loop.

...

else if (aluout==4'd1)  one <=1'b1;

else if (aluout==4'd2)  two <= 1'b1;

...

 

 

or alternate

 

one <= (aluout==4'd1) ?1'b1:1'b0;

 two <= (aluout==4'd2)  ?1'b1:1'b0;

 

 

 

 

-R

 




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10,094 Views
Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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awillen, I am new in this field.

I am trying for last 2 hours but i have failed

 

when ever i get solution for question i automatically accept it.

 

Plz help me for this problem

 

I am very sorry to read what 

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Re: How to declare two bit input in UCF of verilog

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The error messages are telling you that you defined some pins in the .UCF file, but no such pins exist in your design.

 

Does that make sense to you?

 

-- Bob Elkind

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Re: How to declare two bit input in UCF of verilog

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Respected Sir, yes that i have understood but all i want is

 


" i want to have multiplication operation on a and b which are two bits each.
I want to choose the select operation of + - and X by switches of kit

then if the result is 1, LED 1 should glow
if result is 2 other LED should glow

and so on.

 

There is somoe mistake in my verilog Code.if somebody can send me solution then it is ok otherwise i am totally exhasted now.

 

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Mentor awillen
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Registered: ‎11-29-2007

Re: How to declare two bit input in UCF of verilog

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awillen, I am new in this field.

I am trying for last 2 hours but i have failed


 

Don't worry, we really want to help you, and it doesn't matter that you're new. You can ask as many beginner's questions as you want, and nobody will think bad about you.

 

However, just as we have patience with you, you need to have patience with us. That means that you have to carefully read our posts, and if there is something you don't understand, then please ask! And if we ask you something, then either because

  1. we need this information, or
  2. the question is supposed to give you a hint: (i.e., you have to think about it, and just being able to answer it brings you one step closer to the solution)

So don't despair, get some rest, carefully read everything in this post again, and then we'll solve your problem step by step.

 

 


when ever i get solution for question i automatically accept it.

 

That's just my signature. It is automatically added to each of my posts and didn't refer specifically to you.

 

 


 

I am very sorry to read what 

 


That is absolutely not what I have written. I was refering to Bob, not to you.

 



Please google your question before asking it.
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Teacher eteam00
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Re: How to declare two bit input in UCF of verilog

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SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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Sir roym  this concept is also not working

 

 

module alu2bit(aluout,result,a,b,select,zero,one,two,three,four,five,six,seven,eight,nine); 
output [3:0] aluout;        // the result
output [3:0]result;
input [1:0] a,b;         // input a and b 
input [1:0] select;
reg [3:0] aluout,result;
output zero,one,two,three,four,five,six,seven,eight,nine;
always@(a or b)
begin
case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase
if (aluout==4'd0) zero<=1'b0; // no LED will glow
else if (aluout==4'd1) one<=1'b1;
else if (aluout==4'd2) two<=1'b1;
else if (aluout==4'd3) three<=1'b1;
else if (aluout==4'd4) four<=1'b1;
else if (aluout==4'd5) five<=1'b1;
else if (aluout==4'd6) six<=1'b1;
else if (aluout==4'd7) seven<=1'b1;
else if (aluout==4'd8) eight<=1'b1;
else if (aluout==4'd9) nine<=1'b1;
else result=zero; 
end
endmodule

 

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Moderator
Moderator
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Registered: ‎07-30-2007

Re: How to declare two bit input in UCF of verilog

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You forgot the reg.  This works for me.  You will have to assign the one two three etc to the pin in the ucf. 

 

 

module alu2bit(aluout,result,zero,one,two,three,four,five ,six,seven,eight,nine,a,b,select);
output [3:0] aluout,result; // the result
output reg zero;
output reg one;
output reg two;
output reg three;
output reg four;
output reg five;
output reg six;
output reg seven;
output reg eight;
output reg nine;
input [1:0] a,b; // input a and b
input [1:0] select;
reg [3:0] aluout,result;

always@(*)
begin
case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase
zero <= (aluout==4'd0) ? 1'b1:1'b0;
one <= (aluout==4'd1) ? 1'b1:1'b0;
two  <= (aluout==4'd2) ? 1'b1:1'b0;
three <= (aluout==4'd3) ? 1'b1:1'b0;
four <= (aluout==4'd4) ? 1'b1:1'b0;
five <= (aluout==4'd5) ? 1'b1:1'b0;
six  <= (aluout==4'd6) ? 1'b1:1'b0;
seven <= (aluout==4'd7) ? 1'b1:1'b0;
eight <= (aluout==4'd8) ? 1'b1:1'b0;
end
endmodule

 

 

 

 

-R

 




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Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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sir when i synthesize it i get the message

 

 

WARNING:Xst:1306 - Output <result> is never assigned.
WARNING:Xst:737 - Found 4-bit latch for signal <$old_aluout_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 

I have removed result as it is not used in code 

 

after removing result i get this warning message

 

 

WARNING:Xst:737 - Found 4-bit latch for signal <$old_aluout_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 

then when i tell it to generate bit file i get this message

pic attached

 

 

THIS is UCF 

 

 

NET "a<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; //for a input

NET "a<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; //for a input

 

NET "b<0>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; // for b input

NET "b<1>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; // for b input

 

NET "select<0>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; //for select input

NET "select<1>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; //for select input

 

 

NET "one" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "two" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "three" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "four" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "five" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "six" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "seven" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "eight" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

 

 

 

bitfile.jpg
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Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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SIR bit file has been generated now 

and let me check it

 

thanks sir for ur help

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Moderator
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Registered: ‎07-30-2007

Re: How to declare two bit input in UCF of verilog

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I tried to fix the code given and I think it will work as is.  It would be more normal have a clock input and instead of

 

always @ (*);

 

use

 

always @(posedge clk);




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Registered: ‎08-31-2010

Re: How to declare two bit input in UCF of verilog

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Respected Sir,

Thanks my Kit is working now and my problem is solved.

 

I am highly thankful to all other people who helped me

 

I was very much tired.

 

My sincere apologies if i said something harsh.

 

It is b/c of u people that i using this FPGA kit

 

Take care 

 

and thanks to Sir Roym Again

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9,411 Views
Registered: ‎09-20-2010

Re: How to declare two bit input in UCF of verilog

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WARNING:Xst:737 - Found 4-bit latch for signal <$old_aluout_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

 

This warning is pretty crucial.  If you look at this part of the code:

 

case (select)
    2'b00:aluout=a+b; // For addition of two bits
    2'b01:aluout=a-b; // For addition of two bits
    2'b10:aluout=a*b; // For multiplication of two bits
endcase

 

"select" can have four values (2'b00, 2'b01, 2'b10 and 2'b11) and you've only told the system what to do for three of them.  Basically, it doesn't know what to do to "aluout" when "select" is 2'b11, so strange things might start happening.  I'd recommend fixing it.

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Moderator
Moderator
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Registered: ‎07-30-2007

Re: How to declare two bit input in UCF of verilog

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Good point, This was cleaned up in a later thread.

 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/How-to-get-rid-of-warning-from-my-code/td-p/110530

 

-R




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