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9,819 Views
Registered: ‎02-14-2011

How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hello Everyone,

            Can anyone tell me on how to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga?

This is to avoid hold time violation reported by xilinx tool after doing synthsis.

 

Regards

Mahesh

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15 Replies
Xilinx Employee
Xilinx Employee
9,817 Views
Registered: ‎02-09-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Delay can be added only to FPGA input ports.

There are 2 constraints defined.

1. IBUF_DELAY_VALUE - Can be applied to any input or bi-directional signal that is not directly driving a

clock or IOB (Input Output Block) register.

Value is 0 to16. These values do not directly correlate to a unit of time but rather additional buffer delay. This buffer delay is mentioned in datasheets.

Ex: NET "top_level_port_name" IBUF_DELAY_VALUE = value;

2. IFD_DELAY_VALUE - Can be applied to any input or bi-directional signal which drives an IOB (Input

Value is 0 to 8. These values do not directly correlate to a unit of time but rather additional buffer delay. This buffer delay is mentioned in datasheets.

Output Block) register.

 

Ex: NET "

Hope this helps you...

top_level_port_name" IFD_DELAY_VALUE = value;

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9,813 Views
Registered: ‎02-14-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi,

   Thanks for the quick reply.  I actually meant how a hold time violation of 1.56ns be fixed by adding delay buffer in RTL using xilinx ISE tool? Also, is there any way we can fix this issue of hold time violation by increasing the output delay of that particular signal (where hold time violation is reported) in constraints file?

 

Regards

Mahesh

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Xilinx Employee
Xilinx Employee
9,811 Views
Registered: ‎02-09-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

you cant add delay to outputs i.e. obuf.

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9,798 Views
Registered: ‎02-14-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi Krishna,
Can you please eloborate your answer little bit more. Like what is the syntax for inserting delays to outputs. Can you help me with an example?
Regards
Mahesh
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Xilinx Employee
Xilinx Employee
9,794 Views
Registered: ‎02-09-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

As i know, there is no option to add delay to OBUF.

I have a straight question. For which flip-flop in FPGA, you are getting hold violation?

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9,789 Views
Registered: ‎02-14-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi,
Its a D-Flip Flop.

Regards
Mahesh
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Xilinx Employee
Xilinx Employee
9,784 Views
Registered: ‎02-09-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

I mean to say in which scenario you are getting hold violation?

 

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Historian
Historian
9,758 Views
Registered: ‎02-25-2008

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

 


@maheshpenugonda wrote:

Hello Everyone,

            Can anyone tell me on how to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga?

This is to avoid hold time violation reported by xilinx tool after doing synthsis.

 

Regards

Mahesh


 

Is this hold-time violation between two internal flip-flops, or is it on a register connected to an input pin?

 

 

----------------------------Yes, I do this for a living.
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9,731 Views
Registered: ‎02-14-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi,

   This is the exact report i got.

 Slack (hold path):      -1.379ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               hsic_data (PAD)
  Destination:          hub_top_inst/u_utmi_hsic/inst_sp6_fpga_hsic_ddr/inst_ddr_data_rx/rx_ddr_inst/f_data_n (FF)
  Destination Clock:    N625 falling at 0.000ns
  Requirement:          0.300ns
  Data Path Delay:      2.148ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
  Clock Path Delay:     3.802ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

Frequency is 240MHz

and it is DDR operated.

Regards

Mahesh

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6,099 Views
Registered: ‎02-14-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi,
here is the report i got.
Slack (hold path): -1.379ns (requirement - (clock path + clock arrival + uncertainty - data path))
Source: hsic_data (PAD)
Destination: hub_top_inst/u_utmi_hsic/inst_sp6_fpga_hsic_ddr/inst_ddr_data_rx/rx_ddr_inst/f_data_n (FF)
Destination Clock: N625 falling at 0.000ns
Requirement: 0.300ns
Data Path Delay: 2.148ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Delay: 3.802ns (Levels of Logic = 2)
Clock Uncertainty: 0.025ns

Its between a PAD and flop.
Clock Frequency is 240MHz
The core is operated in DDR mode.
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Xilinx Employee
Xilinx Employee
6,085 Views
Registered: ‎01-03-2008

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Your problem is that you have a high frequency input path and you are not using the registers in the IO.  You indicated that this is a DDR interface so your input pad should be connected to an IDDR2 register to capture this data correctly.

 

See UG381 for more details.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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6,064 Views
Registered: ‎02-14-2011

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi,

   Thanks for the suggestion. we however tried this option initally and found set up violations and no hold time violations.

Let me know if there is another best way to do overcome this problem.

 

Regards

Mahesh

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Xilinx Employee
Xilinx Employee
6,054 Views
Registered: ‎01-03-2008

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

> Thanks for the suggestion. we however tried this option initally and found set up violations

> and no hold time violations.

 

So you traded one bad situation for an even worse situation.

 

> Let me know if there is another best way to do overcome this problem.

 

The best way to implement a high speed IO interface is to use the dedicated logic in the IOB.  Attempting to capture a 480 Mbps stream (240 MHz DDR) using a register(s) in the fabric will not work.

 

Please describe your interface and timing requirements in detail and maybe the forum can help you work through the issues.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Highlighted
Visitor brianxilinx
Visitor
5,735 Views
Registered: ‎02-27-2012

Re: How to insert 1.56ns delay buffer in RTL or in constraints file of xilinx spartan fpga

Hi,

I am wondering if anyone is working on High-Speed Inter-Chip USB [HSIC]; a USB chip-to-chip interconnect protocal. Is there any IP, test bench, tets board available?

Thanks,

Tags (1)
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Instructor
Instructor
5,732 Views
Registered: ‎07-21-2009

please start a new thread

@brian,

 

You should open a new thread to begin a discussion of an unrelated topic or question such as this.

 

-- Bob Elkind

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