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Observer binpersonal
Observer
11,933 Views
Registered: ‎08-14-2007

How to invert sampled clock signal?

Dear all,

 

I sampled both clock signal and data signal, want to feed to IDDR2, however it requires two clocks. So my sampled clock

signal can not feed directly to IDDR2, needs an inverted sampled  clock signal,

how to invert it so that the inverted signal without any skew & delay related to  the sampled clock?

 

BTW, I feel spartan is so troublesome, why it need two clock? why it can not have IDDR as virtex?

 

Thank you very much!

 

 

 

 

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23 Replies
Xilinx Employee
Xilinx Employee
11,930 Views
Registered: ‎01-03-2008

Re: How to invert sampled clock signal?

The IDDR2 has local/internal inversion on the clock inputs. Simply invert the clock at the port connection and the software will take care of it.
------Have you tried typing your question into Google? If not you should before posting.
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Observer binpersonal
Observer
11,921 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

can u give me example?

will it produce skew?

 

Thank you very much!

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Xilinx Employee
Xilinx Employee
11,916 Views
Registered: ‎01-03-2008

Re: How to invert sampled clock signal?

>can u give me example?

 

Verilog Example -


   .C0( my_clock),

   .C1(~my_clock),

 

>will it produce skew?

 

No.

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Teacher eteam00
Teacher
11,914 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

In addition to Ed's (mcgett's) reply,  refer to UG381 (v1.4), table 2-2 (on page 54).  Also Figure 2-3 on page 52.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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Observer binpersonal
Observer
11,850 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

Hi, Thank you! but how to use primitives for my_clock and ~my_clock?

because my MAP failed:

 

IDDR2 symbol
"physical_group_*" (*) has its C0 and C1  clock pins driven by the same BUFIO2, but one clock pin is inverted while the
   other is not. This will result in a situation that cannot be supported in the hardware. Please ensure that C0 and C1 have the same polarity when driven by  the same BUFIO2.

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Teacher eteam00
Teacher
11,842 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

Hi, Thank you! but how to use primitives for my_clock and ~my_clock?  because my MAP failed:

Well, this was more fun than I thought...

I tried a quick experiment with ISE12.4 running on WinVista64, and here's what I've found...

 

These work fine:

  • Drive IDDR2 .C0, .C1 from BUFG, using "~ddr_clk" at .C1 input
  • Drive IDDR2 .C0, .C1 from IBUFG, using "~ddr_clk" at .C1 input
  • Drive IDDR2 .C0 from BUFIO2/IOCLK, drive IDDR2 .C1 from 2nd BUFIO2/IOCLK (with I-INVERT="TRUE")

These do not work

  • Drive IDDR2 .C0 from BUFIO2/IOCLK, Drive IDDR2 .C1 from 2nd BUFIO2/IOCLK (with I-INVERT="FALSE")
  • Drive IDDR2 .C0, .C1 from single BUFIO2/IOCLK

Here's my code (with the various options selectively commented out)

 

module s6_adder (
input ddr_inclk,
input ddr_data_in,
output ddrQ_a, ddrQ_b ) ;

//IBUFG #( .IOSTANDARD("LVCMOS33") ) // Specify the input I/O standard
// IBUFG_inst (
// .O (ddr_clk), // Clock buffer output
// .I (ddr_inclk) ); // Clock buffer input (connect directly to top-level port)

BUFG BUFG_inst (
.O (ddr_clk), // 1-bit output Clock buffer output
.I (ddr_inclk) ); // 1-bit input Clock buffer input


//BUFIO2 #(.DIVIDE(1), // DIVCLK divider (1-8)
// .DIVIDE_BYPASS ("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
// .I_INVERT ("FALSE"), // Invert clock (TRUE/FALSE)
// .USE_DOUBLER ("FALSE") ) // Use doubler circuitry (TRUE/FALSE)
//BUFIO2_A (
// .DIVCLK (), // 1-bit output Divided clock output
// .IOCLK (ddr_clk), // 1-bit output I/O output clock
// .SERDESSTROBE (),
// .I (ddr_inclk) ); // 1-bit input Clock input

//BUFIO2 #( .DIVIDE (1), // DIVCLK divider (1-8)
// .DIVIDE_BYPASS ("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
// .I_INVERT ("TRUE"), // Invert clock (TRUE/FALSE)
// .USE_DOUBLER ("FALSE") ) // Use doubler circuitry (TRUE/FALSE)
//BUFIO2_B (
// .DIVCLK (), // 1-bit output Divided clock output
// .IOCLK (ddr_clkn), // 1-bit output I/O output clock
// .SERDESSTROBE (),
// .I (ddr_inclk) ); // 1-bit input Clock input (connect to IBUFG)

IDDR2 #(.DDR_ALIGNMENT ("C0"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0 (1'b0), // Sets initial state of the Q0 output
 .INIT_Q1 (1'b0), // Sets initial state of the Q1 output
 .SRTYPE ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) IDDR2_inst (
.Q0 (ddrQ_a), // 1-bit output captured with C0 clock
.Q1 (ddrQ_b), // 1-bit output captured with C1 clock
.C0 (ddr_clk), // 1-bit clock input
.C1 (~ddr_clk), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D (ddr_data_in), // 1-bit DDR data input
.R (1'b0), .S (1'b0) );

endmodule

- Bob Elkind

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Teacher eteam00
Teacher
11,811 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

Hi, Thank you! but how to use primitives for my_clock and ~my_clock? because my MAP failed:

IDDR2 symbol
"physical_group_*" (*) has its C0 and C1  clock pins driven by the same BUFIO2, but one clock pin is inverted while the other is not. This will result in a situation that cannot be supported in the hardware. Please ensure that C0 and C1 have the same polarity when driven by  the same BUFIO2.

When I try to duplicate your design -- BUFIO2.IOCLK driving IDDR2 .C0 and .C1 inputs, with .C1 inverted internally -- I get two error messages, one of which is similar to the message you quoted:

ERROR:LIT:648 - IDDR2 symbol "physical_group_ddrQ_a_OBUF/IDDR2_inst" (output
   signal=ddrQ_a_OBUF) has pins C0 and C1 driven by the same BUFIO2 or BUFPLL.
   Please modify your design to avoid this unroutable situation.
ERROR:LIT:585 - IDDR2 symbol "physical_group_ddrQ_a_OBUF/IDDR2_inst" (output
   signal=ddrQ_a_OBUF) has its C0 and C1 clock pins driven by the same BUFIO2,
   but one clock pin is inverted while the other is not. This will result in a
   situation that cannot be supported in the hardware. Please ensure that C0 and
   C1 have the same polarity when driven by the same BUFIO2.

The first error message (unroutable) seem plausible, but the second seems like a software bug.  If it isn't a software bug, then either I'm reading UG381 (v1.4) Table 2-2 incorrectly or UG381 is leading me astray.


If I replace the BUFIO2 with either a BUFG or IBUFG (keeping the IDDR2.C1 input inversion), I get no error or warning messages.

 

-- Bob Elkind

SIGNATURE:
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Observer binpersonal
Observer
11,780 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

Thank you, eteam00,

 

But it doesn't seem  to work in timing. I check the timing report, the data pair doesn't appeal at Q0 and Q1 pin at the same time,  one is delayed  more than one clock cycle compared to the other,  porbably due to the inverted clock signal.

 

Could you have a look?

 

 

 

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Teacher eteam00
Teacher
11,775 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

But it doesn't seem  to work in timing. I check the timing report, the data pair doesn't appeal at Q0 and Q1 pin at the same time,  one is delayed  more than one clock cycle compared to the other,  porbably due to the inverted clock signal.

I'm skeptical.  Which clock distribution scheme are you using?  Is this simulated results, or scope-measured results?

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Observer binpersonal
Observer
8,262 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

Thanks, I  sampled both DDR clock and data, then use BUFG primitive to buffer sampled DDR clock to drive IDDR2.

 

I ran Timing Analyzer ( Tools-> Timing Analyzer-> Post-Map), from timing report, I can see the data delay from Q0 and Q1 are

not almost the same, but has large delays between them. 

 

 

>I'm skeptical.  Which clock distribution scheme are you using?  Is this simulated results, or measured  results?

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Teacher eteam00
Teacher
8,260 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?


binpersonal wrote:

Thanks, I  sampled both DDR clock and data, then use BUFG primitive to buffer sampled DDR clock to drive IDDR2.


I ran Timing Analyzer ( Tools-> Timing Analyzer-> Post-Map), from timing report, I can see the data delay from Q0 and Q1 are not almost the same, but has large delays between them.


Please post the relevant sections of the timing report, and the IDDR2 port connections.  The timing report results and the map error message you've gotten both seem to contradict information posted in these forums by knowledgeable Xilinx support folks.  I'm not a Xilinx employee, but I'm pretty sure this will get some attention from the folks at Xilinx who understand what's going on.  I'm looking forward to it.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer binpersonal
Observer
8,251 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

Below is selected from the timing report, read_data0 is connected to Q1 (delay is 1.229ns) , read_data1 is connected to Q0 (delay is 4.569ns), the difference between delays are 4.569-1.229 = 3.34 ns, it is larger than 2.5ns, which is the period of  DDR clock and connected to C1, an inverted DDR clock  is connected to C0 of IDDR2.

 

 

 

  Maximum Data Path at Slow Process Corner: ddrif_inst/data_path_iobs_0/IDDR2_inst_<3> to ddrif_inst/data_path_iobs_0/Mshreg_shf_reg_2_1

Location             Delay type                      Delay(ns)                                    Physical Resource
                                                                                                                           Logical Resource(s)
     ------------------------------------                  -------------                                        ------------------- 

ILOGIC_X3Y117.Q4     Tickq                         1.229           ddrif_inst/data_path_iobs_0/read_data0<3>
                                                                                                 ddrif_inst/data_path_iobs_0/IDDR2_inst_<3>
SLICE_X22Y109.DX     net (fanout=1)     e  4.569          ddrif_inst/data_path_iobs_0/read_data1<3>

SLICE_X22Y109.CLK    Tds                         -0.100         ddrif_inst/data_path_iobs_0/shf_reg_2<9>
                                                                                                ddrif_inst/data_path_iobs_0/Mshreg_shf_reg_2_1
     -------------------------------------------------  ---------------------------
     Total                                                            5.698ns (1.129ns logic, 4.569ns route)
                                                                                         (19.8% logic, 80.2% route)
 
 -------------------

 

 

>Please post the relevant sections of the timing report, and the IDDR2 port connections.  The timing report results and the >map error message you've gotten both seem to contradict information posted in these forums by knowledgeable Xilinx >support folks.  I'm not a Xilinx employee, but I'm pretty sure this will get some attention from the folks at Xilinx who >understand what's going on.  I'm looking forward to it.

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Teacher eteam00
Teacher
8,238 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

Hmmm...

 

Most of the delay you are seeing is in ROUTE delay from register Q to the next register input, not logic delay.

And maybe I'm misreading your output report, but either parts of two different path are reported, or only one path report is shown.  I would expect to see two sets of Tickq, net, and Tds numbers, not one.

 

here are the results of my quick/dirty test design, showing close matching of clk => output delays.

 

 Clock ddr_inclk to Pad 
 -------+----------+-------+----------+-------+--------+--------+
        |Max       |       |      Min |       |        |        |
        |(slowest) |       | (fastest)|       |        |        |
 Desti  |clk (edge)|Process|clk (edge)|Process|Internal| Clock  |
 nation |  to PAD  | Corner|  to PAD  | Corner|Clock(s)| Phase  |
 -------+----------+-------+----------+-------+--------+--------+
 ddrQ_a |  9.932(R)|  SLOW |  3.932(R)| FAST  |ddr_clk |   0.000|
 ddrQ_b | 10.423(R)|  SLOW |  4.161(R)| FAST  |ddr_clk |   0.000|
 -------+----------+-------+----------+-------+--------+--------+

 This is with Spartan6 target, of course.

 

- Bob Elkind

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Observer binpersonal
Observer
8,232 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

I think two different path are reported in my report:  read_data0<3>  and  read_data1<3>, the discrepancy between them is larger then 1 clock period.

 

And how to display table like yours?

 

>Most of the discrepancy you are seeing is in ROUTE delay from register Q to the next register input, not logic delay.

>And maybe I'm misreading your output report, but either parts of two different path are reported, or only one path report is >shown.  I would expect to see two sets of Tickq, net, and Tds numbers, not one.

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Teacher eteam00
Teacher
8,229 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

Below is selected from the timing report, read_data0 is connected to Q1 (delay is 1.229ns) , read_data1 is connected to Q0 (delay is 4.569ns), the difference between delays are 4.569-1.229 = 3.34 ns, it is larger than 2.5ns, which is the period of  DDR clock and connected to C1, an inverted DDR clock  is connected to C0 of IDDR2.

The meaningful timing paths are:

  • DDR_Din setup to rising edge of DDR_clock
  • DDR_Din setup to falling edge of DDR_clock

If there are any mismatched clock delays in the paths to the IDDR2 registers (due to unmatched inverter delays, for example), these two paths (above) are where the mismatches would appear.

 

Here are the results for these paths, for my quick/dirty experiment:

 

 Setup/Hold to clock ddr_inclk 
 ------------+------------+-------+------------+-------+--------+-----+ 
             |Max Setup to|Process|Max Hold to |Process|Internal|Clock| 
 Source      | clk (edge) |Corner | clk (edge) |Corner |Clock(s)|Phase| 
 ------------+------------+-------+------------+-------+--------+-----+ 
 ddr_data_in |   -0.319(R)| FAST  |    1.957(R)| SLOW  |ddr_clk |0.000| 
             |   -0.319(F)| FAST  |    1.957(F)| SLOW  |ddr_clk |0.000| 
 ------------+------------+-------+------------+-------+--------+-----+ 

 

Internal to the IDDR2 block, the two "phases" of captured data are aligned to .C1 input clock, by following the output of the register clocked by .C0 input clock with a register clocked by .C1 input clock.  See UG381 figure 2-7.  At the output of the IDDR2 block, both Q0 and Q1 should be indistinguishable.

 

- Bob Elkind

SIGNATURE:
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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Teacher eteam00
Teacher
8,226 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

I think two different path are reported in my report:  read_data0<3>  and  read_data1<3>, the discrepancy between them is larger then 1 clock period.

What you posted is clearly a single path.

 

Why don't you post your source code showing the connections to the IDDR2 block, and it will be simple enough to point out one path from another.

 

In any case, the path delay following the output of the IDDR2 block has nothing to do with clock inversion delay (or no delay).

 

- Bob Elkind

SIGNATURE:
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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Teacher eteam00
Teacher
8,225 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

And how to display table like yours?

I used the Timing > Run Analysis tool from within ISE Navigator.  I manually reformatted the report so it would fit in the forum message window without line wrapping.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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Teacher eteam00
Teacher
8,215 Views
Registered: ‎07-21-2009

Executive Summary for this thread, to Xilinx Support folks

This thread has covered some inconsistencies with how IDDR2 is handled in ISE12.4, and it has covered some (probable) confusion on the part of the original poster.

 

For the Xilinx support folks who might be reading this, here is the EXECUTIVE SUMMARY (so far) for this thread.

 

When driving IDDR2 .C0, .C1 from a single BUFIO2/IOCLK output with IDDR2.C1 inverted internally -- I get two error messages:

ERROR:LIT:648 - IDDR2 symbol "physical_group_ddrQ_a_OBUF/IDDR2_inst" (output
   signal=ddrQ_a_OBUF) has pins C0 and C1 driven by the same BUFIO2 or BUFPLL.
   Please modify your design to avoid this unroutable situation.
ERROR:LIT:585 - IDDR2 symbol "physical_group_ddrQ_a_OBUF/IDDR2_inst" (output
   signal=ddrQ_a_OBUF) has its C0 and C1 clock pins driven by the same BUFIO2,
   but one clock pin is inverted while the other is not. This will result in a
   situation that cannot be supported in the hardware. Please ensure that C0 and
   C1 have the same polarity when driven by the same BUFIO2.

The first error message (unroutable) seem plausible, but the second seems like a software bug.  If it isn't a software bug, then either I'm reading UG381 (v1.4) Table 2-2 incorrectly or UG381 is leading me astray (where it says both .C0 and .C1 inputs are invertible).


If I replace the BUFIO2 with either a BUFG or IBUFG (keeping the IDDR2.C1 input inversion), I get no error or warning messages.

 

I could be wrong, but I think I've done my good deed for the day...

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Observer binpersonal
Observer
8,197 Views
Registered: ‎08-14-2007

Re: How to invert sampled clock signal?

And how to see " Setup/Hold to clock ddr_inclk" after Timing> Run Analysis?  

 

I used the Timing > Run Analysis tool from within ISE Navigator.  I manually reformatted the report so it would fit in the forum message window without line wrapping.

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Teacher eteam00
Teacher
4,852 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

And how to see " Setup/Hold to clock ddr_inclk" after Timing> Run Analysis?

In the Design Summary pane, select Design Overview > Static Timing

 

- Bob Elkind

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: How to invert sampled clock signal?

> Thanks, I  sampled both DDR clock and data, then use BUFG primitive to buffer sampled DDR clock to drive IDDR2.

 

Your description is quite unusual.  Bob asked you to post your source code, please do this.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer emounty
Observer
4,619 Views
Registered: ‎10-27-2008

Re: How to invert sampled clock signal?

Device: S6LX45T

toolset:  ISE12.1 M.53d  AND Project Navigator 13.2 O.61xd

problem:

 

Same source file( very simple clock forwarding), same device, two toolsets with process properties the same( as close as possible between the tools).

 

12.1 implementation runs fine.

13.2 MAP error

 

"ERROR:LIT:651 - ODDR2 symbol "physical .. " has pins C0 and C1 driven by the same BUFIO2 or BUFFPLL ...situation.

 

Why such a big difference in tool response? 

 

 

 

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Teacher eteam00
Teacher
4,615 Views
Registered: ‎07-21-2009

Re: How to invert sampled clock signal?

Please do NOT post an unrelated topic or question to an existing thread.  Instead, start a new thread, and keep the two topics separate.  I've included a followup to your post.  If this does not resolve the issue for you, then please start a new thread to continue this discussion.

 

Same source file( very simple clock forwarding), same device, two toolsets with process properties the same( as close as possible between the tools).

 

12.1 implementation runs fine.

 

Try running BITGEN.  I predict that BITGEN will fail with a DRC error.

 

13.2 MAP error

 

"ERROR:LIT:651 - ODDR2 symbol "physical .. " has pins C0 and C1 driven by the same BUFIO2 or BUFFPLL ...situation.

 

I believe you've come across a bug in the 12.x release, where MAP erroneously permits BUFIO2 to drive both .C0 and .C1 pins of ODDR2 block.  The design rule violation isn't caught until BITGEN runs.

 

If you want to drive .C0 and .C1 clock pins from a single clock net (a perfectly reasonable implementation), the clock must be driven by a BUFG -- not an IBUFG, not a BUFIO2, not a BUFPLL.  Try this, and see how it works for you.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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