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Explorer
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Registered: ‎07-03-2014

How to span a clock to multiple clock regions using HCLK resources?

Hello everybody,

 

I've been programming in VHDL for Spartan-6 for a couple of years in high-end projects. Seeing as the project complexity has grown exponentially in the last month, I've ended up by using all available BUFG resources.

My proposed solution is to implement one module in a clock region in order to use HCLK routing resources through BUFH. My problem is the module doesn't fit in only one clock region but it occupies two consecutives of them. The VHDL for the module is more than 1000 lines length and it has 25 different processes, making it difficult to change each process clock into the regional clocks, besides it would be a less optimal implementation. My question is: how can I easily change my VHDL so the mapper infers as many BUFH as necessary to implement the module in two consecutive clock regions?

 

Thanks!

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Re: How to span a clock to multiple clock regions using HCLK resources?

Hi Alex,

I don't think there is a switch in implementation tool to auto-insert the BUFH intelligently.

What you can do is, use the attribute- buffer_type on the clock nets on which you plan to insert BUFH.

You can find more information on buffer type attribute in page 383 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf

Regards,
Krishna
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Registered: ‎07-03-2014

Re: How to span a clock to multiple clock regions using HCLK resources?

Hi, smarell.

I was trying to avoid modifying the VHDL from this:

PRC1 : Process( clk )
Begin
   .....
End


PRC2 : Process( clk )
Begin
   .....
End


PRC3 : Process( clk )
Begin
   .....
End

 

... to this:

 

CLK_RG0 : BUFH( I => clk, O => clk_RG0);
CLK_RG1 : BUFH( I => clk, O => clk_RG1);

PRC1 : Process( clk_RG0 ) Begin ..... End PRC2 : Process( clk_RG0 ) Begin ..... End PRC3 : Process( clk_RG1 ) Begin ..... End

 

By doing this, it's very likely I will not be separating logic between clock regions optimally, so maybe the design will occupy more slices and won't ft in the FPGA.

 

Thanks very much for your answer, smarell.

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Community Manager
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Registered: ‎07-23-2012

Re: How to span a clock to multiple clock regions using HCLK resources?

Hi,

Driving the slices with different clocks is not enough to ensure that they would be placed in different clock regions. There are additional factors that would determine the placement of these slices.

Dividing the clocks using two BUFHs won't increase the no. of slices because we are not actually changing the logic instead we are just changing the clock that is driving them.

Regards,
Krishna
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Registered: ‎07-03-2014

Re: How to span a clock to multiple clock regions using HCLK resources?

Yes, I also added UCF constraints to ensure each process is placed in a different clock region:

INST "MODULE/PRC1" AREA_GROUP = "CLKAG_PRC1" ;
AREA_GROUP "CLKAG_PRC1" RANGE = CLOCKREGION_X1Y4 ;

INST "MODULE/PRC2" AREA_GROUP = "CLKAG_PRC2" ;
AREA_GROUP "CLKAG_PRC2" RANGE = CLOCKREGION_X1Y4 ;
INST "MODULE/PRC3" AREA_GROUP = "CLKAG_PRC3" ;
AREA_GROUP "CLKAG_PRC3" RANGE = CLOCKREGION_X1Y5 ;

 

That is a bit tedious, so my question was about whether there was a way to do it easily or not.

If it could be as easy as this, it would be great:

 

INST "MODULE/*" AREA_GROUP = "CLKAG_MODULE" ;
AREA_GROUP "CLKAG_MODULE" RANGE = CLOCKREGION_X1Y4 : CLOCKREGION_X1Y5;

 

Thanks again for your interest.

 

Cheers!

 

INST "PRC1" AREA_GROUP = "CLKAG_PRC1" ;

AREA_GROUP "CLKAG_PRC1" RANGE = CLOCKREGION_X1Y4 ;

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