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rhockenblue
Newbie
Newbie
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Registered: ‎06-06-2009

How to use the DDR tristate mux in the IOB?

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Looking at the IOB structure for the Spartan-3 (Fig10.1 UG331), It shows the tristate path as having DDR functionality much the same as the data path. What I want to do (simplified a bit) is have T1='1', T2='0', clock onto OTCLK1, 180deg version onto OTCLK2, and O1 bypassing the Data DDR componentry. This should only drive the output for second half of the cycle. i.e. if OTCLK1 is 100MHz, then the output pin will be driven for the 5ns at the end of each cycle.

 

The reason I want to do this is to interface to an SRAM and have quick read->write transitions. The data for the write only needs to be present for the second half of the cycle (for >=5ns), it shouldn't be driven for the first half of the cycle because the SRAM may not have released the databus yet.

 

It says in the documentation, that DDR output functionality can not be infered - it must be explicit. The OFDDRSE element is available for the data path in the IOB, but I can not find a more 'complete' element which also includes the Tristate path (OFDDRTRSE only has the simple tristate path). I tried using the OFDDRSE and using it to control the enable on the tristate and unsurprisingly it wouldn't work. CoreGen didn't have anything either.

 

Is there a core element I can use to expose this functionality? And if not how is anyone supposed to use this feature?

 

thanks

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rhockenblue
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Registered: ‎06-06-2009

---Solved it already ---

 

I Looked in UG608 (Spartan3 Libraries guide for Schematic Designs) and there is a FDDRCPE which I can connect to the tristate enable and it synthesises properly. This is not listed in UG607 (Spartan3 Libraries guide for HDL designs).

 

Given I'm working in VHDL I didn't think to look in the schematic guide (or more so I thought the information would be the same). Using FDDRCPE in VHDL worked correctly, and I could confirm it by looking at the FPGA editor.

 

Guess I'll leave this post here incase any one else searches for it.....

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rhockenblue
Newbie
Newbie
5,245 Views
Registered: ‎06-06-2009

---Solved it already ---

 

I Looked in UG608 (Spartan3 Libraries guide for Schematic Designs) and there is a FDDRCPE which I can connect to the tristate enable and it synthesises properly. This is not listed in UG607 (Spartan3 Libraries guide for HDL designs).

 

Given I'm working in VHDL I didn't think to look in the schematic guide (or more so I thought the information would be the same). Using FDDRCPE in VHDL worked correctly, and I could confirm it by looking at the FPGA editor.

 

Guess I'll leave this post here incase any one else searches for it.....

View solution in original post

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