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Visitor bmarkey
Registered: ‎12-31-2009

IO standard for 62MHz 9-bit wide backplane


I am trying to migrate a Spartan 3 design using GTLP to Spartan 6 and am wondering if anyone has used the HSTL or SSTL IO standards across a standard parallel backplane.  Obviously Xylinx is pushing GBT but at the data rate I am running that is overkill and I would have to reconnectorize the backplane interface.  Since support is closed today I decided to see if anyone here is working today. 

Here are my thoughts on approaches:

CMOS-pusing the limits on speed with 5 boards on the bus and 62 MHz rate with 9 parallel bits of data.  May work but would be noisy and SSO requirements may limit practicality


SSTL-designed for memory interface but may provide enough current for my application


HSTL-similar to SSTL but a higher current is available, may be required for my application due to low loaded impedance, probably close to 40 ohms.


Thanks for any input you have.

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Teacher drjohnsmith
Registered: ‎07-09-2009

Re: IO standard for 62MHz 9-bit wide backplane

Do you have to use parallel ?


A differential pair using the IOSERDES of the spartan 6 would be fast. 


Not certain about Gunning logic over a backplane, the terminatino could be interesting varied depending upon the amount of boards plugged in.


I've a 144 GTL+ bit bus running at 130 MHz around 6  Virtex chips on a board running very well.


 Do you have the capability to go differential ?

    do you want a true bus , i.e. any to any, or is it one to many ?


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Registered: ‎07-27-2009

Re: IO standard for 62MHz 9-bit wide backplane

Have you considered PCI buffers at 62MHz?
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