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Visitor mheld
Visitor
10,197 Views
Registered: ‎03-01-2011

ISE not packing in Spartan 3A

Good day,

 

I have a design I'm trying to get fit into a Spartan 3AN/50.  It's failing at MAP as though the entire device is being overutilzed.  However, it's not packing unrelated logic into slices it would seem. 

 

Logic Distribution:
  Number of occupied Slices:            752 out of     704  106% (OVERMAPPED)
    Number of Slices containing only related logic:     752 out of     752 100%
    Number of Slices containing unrelated logic:          0 out of     752   0%

 

Am I missing a switch, or is this device simply too small for what I want?  I'm only using 60% of resources otherwise (Flipflops and LUTs, the rest attached below)  Or is there some reason it's leaving a large number of LUTs/FF's unused and not packing unrelated logic into slices?  (Perhaps a SliceL says 'dont bother packing anything else into this device'?)  Timing for this is currently not an issue, it's coming out of P&R at twice the speed we need.

 

I understand how slice packing is sparse to begin with, and I've searched around, but haven't found any reason why it wouldn't continue packing into slices.  This is ISE Web 13.3 lin64 (0.76xd).

 

If I can't fit the design into the device as is, it's not the end of the world, just need some redesigning / respecifying.

 

Thanks,

Martin

 

 

Pack:2310 - Too many comps of type "SLICEL" found to fit this device.

Logic Utilization:
  Number of Slice Flip Flops:           826 out of   1,408   58%
  Number of 4 input LUTs:               883 out of   1,408   62%
Logic Distribution:
  Number of occupied Slices:            752 out of     704  106% (OVERMAPPED)
    Number of Slices containing only related logic:     752 out of     752 100%
    Number of Slices containing unrelated logic:          0 out of     752   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         934 out of   1,408   66%
    Number used as logic:               882
    Number used as a route-thru:         51
    Number used as Shift registers:       1

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

 

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11 Replies
Instructor
Instructor
10,194 Views
Registered: ‎08-14-2007

Re: ISE not packing in Spartan 3A

Map has a -cm switch called "Optimization Strategy (cover mode)" in the GUI.  If this is off, you won't get

any unrelated packing.  Normally you should try to set it to "Area" or "Speed" to find a setting that might work.

 

XST also has optimization settings, which you could try to tweak if you can't get enough out of

map.

 

-- Gabor

-- Gabor
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Visitor mheld
Visitor
10,188 Views
Registered: ‎03-01-2011

Re: ISE not packing in Spartan 3A

-cm is set by default to Area.  I tried monkeying with all the settings that I thought might help, including having it intentinally use a 1% slice ratio in XST and MAP (tries to force packing into slices, though the documentation basicaly says "This should only be used to determine what the minimum area for a design will be, your timing is going to suck."  I eventually reverted all the XST/Implementation options to defaults.

 

I tried setting -cm to Speed, Balanced, and Off, and they all produce the same results as Area, 752/704 slices used/overmapped.  (Fortunately it's a relatively small design, so re-running MAP doesn't take long).  Anything else I might be able to try?

 

Cheers,

Martin

 

 

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Instructor
Instructor
10,184 Views
Registered: ‎08-14-2007

Re: ISE not packing in Spartan 3A

Unless there is something about the design that prevents unrelated packing, I would assume

that 65% of LUTs and FFs should fit into 100% of the slices.  Another suggestion, since this is

not a new part and may not have been well tested in the most recent ISE version, would be to

back up to ISE 12.4 and see if it does better.  Other than that, if you have spare block RAM

you can "map slice logic into unused block RAMs" but I wouldn't expect to get a reduction of

50 slices that way.

 

-- Gabor

-- Gabor
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Visitor mheld
Visitor
10,182 Views
Registered: ‎03-01-2011

Re: ISE not packing in Spartan 3A

Hmm.  I have 12.1 installed on my computer at home, might have 12.1 sitting around somewhere too that I can install on a spare linux copy on my work computer's VM.  I'll give that a try too since I'm here.  Will have to do after my 2:30 meeting though.

 

Do you know what reasons there might be that the 65% of LUT/s FF's can't fit into 100% of slices?  I don't know what conditions can block packing.  That said, I would think at least *one* slice would have unrelated logic, but I'm getting none as shown in the report.

 

Thanks for your assitance,

Martin

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Instructor
Instructor
10,178 Views
Registered: ‎08-14-2007

Re: ISE not packing in Spartan 3A

That said, I would think at least *one* slice would have unrelated logic, but I'm getting none as shown in the report.

 

That's a good reason to suspect tools rather than your design.  It would be a very unusual design

that could not have any unrelated logic packed into the same slice.  Either there is something

else in the ISE 13.x settings that is preventing the packing (a new switch?) or there really is

some unrelated packing (a new definition of related?) or the tools are hopelessly broken...

 

On the other hand, looking through my recent projects with S3A parts I don't see any unrelated packing

going on, although none of them are nearly full.  So maybe this issue was already around well

before ISE 13.x (I'm still using 12.4 but some of the "recent" projects go back to ISE 9.1i).

 

It might be time to start a webcase on this one...

 

-- Gabor

-- Gabor
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Visitor mheld
Visitor
10,173 Views
Registered: ‎03-01-2011

Re: ISE not packing in Spartan 3A

Well, I'll give 12.4 a try first and go from there.

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Xilinx Employee
Xilinx Employee
10,167 Views
Registered: ‎11-28-2007

Re: ISE not packing in Spartan 3A

Can you post the entire logic utilization section from the map report showing % of all logic utilization and notes?
Cheers,
Jim
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Visitor mheld
Visitor
10,148 Views
Registered: ‎03-01-2011

Re: ISE not packing in Spartan 3A

Sure, here's the entire thing.  Didn't want to spam it all before, but here it is for your enjoyment!

 

It says 0% unrelated logic, but also odd is that it's packing into 759 SliceL's, though it clearly needs 8-900 LUT's & FF's.  Some of that might be IO FF's and stuff, not sure, but the numbers are still odd.  Depending on what switches I use, I can get to 751 SliceL's, this particular run was likely something non-optimal.

 

Thanks,

Martin

 

 

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc3s50a-tq144-4 -cm area -detail -ir off -pr off -c 1 -o endpointExample2_map.ncd endpointExample2.ngd endpointExample2.pcf
Using target part "3s50atq144-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Running unrelated packing...
Updating timing models...
ERROR:Pack:2310 - Too many comps of type "SLICEL" found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.
   Please check the Design Summary section to see which resource requirement for
   your design exceeds the resources available in the device.

   NOTE: An NCD file will still be generated to allow you to examine the mapped
   design.  This file is intended for evaluation use only, and will not process
   successfully through PAR.

   This mapped NCD file can be used to evaluate how the design's logic has been
   mapped into FPGA logic resources.  It can also be used to analyze
   preliminary, logic-level (pre-route) timing with one of the Xilinx static
   timing analysis tools (TRCE or Timing Analyzer).

Design Summary:
Number of errors:      2
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           832 out of   1,408   59%
  Number of 4 input LUTs:               893 out of   1,408   63%
Logic Distribution:
  Number of occupied Slices:            759 out of     704  107% (OVERMAPPED)
    Number of Slices containing only related logic:     759 out of     759 100%
    Number of Slices containing unrelated logic:          0 out of     759   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         944 out of   1,408   67%
    Number used as logic:               891
    Number used as a route-thru:         51
    Number used as Shift registers:       2

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 63 out of     108   58%
    IOB Flip Flops:                       1
  Number of BUFGMUXs:                     2 out of      24    8%

Average Fanout of Non-Clock Nets:                3.50

Peak Memory Usage:  601 MB
Total REAL time to MAP completion:  10 secs
Total CPU time to MAP completion:   6 secs

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "endpointExample2_map.mrp" for details.
Problem encountered during the packing phase.

Process "Map" failed


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Visitor mheld
Visitor
10,142 Views
Registered: ‎03-01-2011

Re: ISE not packing in Spartan 3A

As an update,

 

I just installed ISE 12.4, and created a new project and copied all the VHDL files over.  100% defaults, and I get nearly the exact same MAP error, so it's not a difference between 13.3 and 12.4.  Mainly, I just need to understand why it's getting overmapped, so that I can ensure I'm not doing something wrong, or that I can better understand design size constraints for future designs.  (We have another design coming up in a Spartan 3AN/50 simply because it's quick and easy for me and I know most of the quirks... Most :). Without tweaks, it came out to 769 SliceL's, and after twiddling a few options for area, packing, etc, got it down to 752 or so just like 13.3.

 

Cheers,

Martin

 

 

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Newbie minikora
Newbie
2,617 Views
Registered: ‎05-07-2013

Re: ISE not packing in Spartan 3A

It seems I'm facing the same problem as yours. How do u overcome the problem ?
Thank you.

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Newbie k@rishma_
Newbie
1,215 Views
Registered: ‎07-22-2017

Re: ISE not packing in Spartan 3A

i'm also getting the same error while mapping. did u get solution for this error??

 

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