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11,283 Views
Registered: ‎06-29-2009

Icap fall-back detection. BOOTSTS

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Hi,

 

I am using the fall-back system on the Spartan 6 (SP605 board).  Reboot and fallBack works fine but:

 

In the flash I have:

    at 0x0000 the start of my Golden Image

    at 0xC000 the start of another image

 

In the golden image i have some functions that can : retrieve info from ICAP and Reboot the FPGA from a choosen address (they work welll and are based on the demo of Xilinx ICAP drivers)

The sequence is :

  - Boot from 0x000 = golden image

  -  Read out the status if ICAP (BOOTSTS = 1)

  -  Reboot from address 0xC0010   (which should simulate a wrong bitstream ... and it does)

  -  fall - Back mechanisme restarts the golden image

  - again read out status (here I expect BOOTSTS has incrementen , but it is still = 1)

 

I also set the "-g next_config_register_write:Disable"  and (-g Reset_on_err:yes) in bitgen.UT

 

I didn't understand neither how to use the scratchpad GENERAL5 register.  It's just a register where you can write something and reuse later to make desissions ... or can you use it to setup some behaviour of the ICAP.

 

In only need my golden image to know if aftere loading the NEW image (0xC0000) it did fall-back to the golden image.

 

Does someone now what I do wrong ... or is my interpretation of this fall-back mechanisme wrong?

 

Thanks!

 

Serge

 

 

 

PS:  I give the output before and after the fallback (but it's the same)  as well as my bitgen settings ... here at the end.

 

 

BITGEN:

 

-g StartUpClk:CCLK
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable

-g Reset_on_err:yes
-g next_config_register_write:Disable

-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g multipin_wakeup:No
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

 

Output:

 

When we start the FPGA power up or program:


CRC ->          0

 FAR_MIN ->      BEEF

 FAR_MAJ ->      BEEF

 FDRI ->         BEEF

 FDRO ->         FFFF

 CMD ->          0

 CTL ->          81

 MASK ->         FF

 STAT ->         373C

 LOUT ->         BEEF

 COR1 ->         3D00

 COR2 ->         89EE

 PWRDN_REG ->    881

 FLR ->          BEEF

 IDCODE ->       14028093

 CWDT ->         FFFF

 HC_OPT_REG ->   1F

 MODE_REG ->     103

 SEU_OPT ->      1BE2

 EXP_SIGN ->     0

 RDBK_SIGN ->    A946

 BOOTSTS ->      1

 EYE_MASK ->     0

 

When 0xC0010 failed:

 

CRC ->          0

 FAR_MIN ->      BEEF

 FAR_MAJ ->      BEEF

 FDRI ->         BEEF

 FDRO ->         FFFF

 CMD ->          0

 CTL ->          81

 MASK ->         FF

 STAT ->         373C

 LOUT ->         BEEF

 COR1 ->         3D00

 COR2 ->         89EE

 PWRDN_REG ->    881

 FLR ->          BEEF

 IDCODE ->       14028093

 CWDT ->         FFFF

 HC_OPT_REG ->   1F

 MODE_REG ->     103

 SEU_OPT ->      1BE2

 EXP_SIGN ->     0

 RDBK_SIGN ->    A946

 BOOTSTS ->      1

1 Solution

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Xilinx Employee
Xilinx Employee
13,970 Views
Registered: ‎08-28-2007

Re: Icap fall-back detection. BOOTSTS

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Hi Serge,

 

Please see the following AR -

 

http://www.xilinx.com/support/answers/37910.htm

 

This should answer your questions I think.

 

-Paul

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Xilinx Employee
Xilinx Employee
13,971 Views
Registered: ‎08-28-2007

Re: Icap fall-back detection. BOOTSTS

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Hi Serge,

 

Please see the following AR -

 

http://www.xilinx.com/support/answers/37910.htm

 

This should answer your questions I think.

 

-Paul

View solution in original post

Highlighted
11,232 Views
Registered: ‎06-29-2009

Re: Icap fall-back detection. BOOTSTS

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Hi Paul,

 

Thanks for your reply .  This clarify the problem. 

 

Greetings,

 

Serge

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Explorer
Explorer
10,895 Views
Registered: ‎11-27-2008

Re: Icap fall-back detection. BOOTSTS

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Hi,

 

Thanks for the information, and I have a related question. What about the WBSTAR register? If I use this do a 'warm boot' can I read it after the reconfiguration to see which load was configured? Even so, I suppose this might not work in the case of a fallback since WBSTAR would still show the previously attempted 'warm boot'?

 

I believe we are trying to accomplish the same thing, allowing the FPGA to see which configuration was loaded, and if it was a Fallback. How can I use the GENERAL5 register to save this information?

 

Thanks for any help.

 

Regards,

Dan

 

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Explorer
Explorer
10,895 Views
Registered: ‎11-27-2008

Re: Icap fall-back detection. BOOTSTS

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Hi,

Just a bit more information.....I am using Virtex5 so do these ARs apply to it as well? They only mention Spartan 6.

Regards,
Dan
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Highlighted
10,876 Views
Registered: ‎06-29-2009

Re: Icap fall-back detection. BOOTSTS

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Hello,

 

I implemented both for spartan6 and Virtex5 .... but it's different.  The ICAP of Spartan is 16bit , while for Virtex5 its 32 .... and the commands are slightly different.

For the General5 register :  the idea is that you write a value in it .... by yourself.   Later you can read this ...

I actualy did the same , but by using the BPI flash ... this provide even more controll, even when the power goes off for one or other reason.   I don't know about General5 on the Virtex5 actualy... that one I only tested in Spartan6.

 

But the idea could be:

   -  Write something in General5 or other memory(eg flash) before you reboot .   I write value "1"

   -  Reboot your FPGA with the new design ....

   -  If the new design works ..... it should change the value "1"  into value "2"  (or wathever you want... you can also do nothing)

   -  If the new design doesnt work,  then it will fallback to the old one  ....   The old design will have to read the General5 or so ....  and if it reads "1"  it means that you failed running the new design.    

 - If your new design works :  make that design write a "2" .... then when you reboot again, it will know that you have previously succesfully runned your new design.

- if you power cycle your fpga board and are using only general5 ... then the value will disapear

 

But several scenarios are possible to do this, it depends what you want to achieve.  This is just one quickly written

 

 

Good luck,

 

Serge

 

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Explorer
Explorer
10,857 Views
Registered: ‎11-27-2008

Re: Icap fall-back detection. BOOTSTS

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Thanks that helps. I don't think Virtex 5 has the General5 register, however, I can use an external NVRAM to record which load was 'attempted'. However, this doesn't tell me if a Fallback occurred, unless my Fallback load is specifically different than the other loads, which I'd rather not have. I'm looking into reading the BOOTSTS register to find out if a fallback happened. I have a webcase open for that since it's not working yet.

Regards,
Dan
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Observer
Observer
10,797 Views
Registered: ‎06-20-2011

Re: Icap fall-back detection. BOOTSTS

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Hi,

I am trying to read Spartan-6 LX BOOTSTS register over ICAP, but I always get the IDCODE register values out of ICAP.  I am using x8 interface currently and I my attempt has been to replicate the sequence described in ug380 p. 109 and 110. Can anyone send me a working sequence? 

Rgds,

Janne

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10,786 Views
Registered: ‎06-29-2009

Re: Icap fall-back detection. BOOTSTS

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i can post you the sequence for x1 , that I used for the spartan sp605 board .... if that helps?  (i'll do later when i am at my office PC)

 

which board are you using?

 

grtz,

 

serge

 

 

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Observer
Observer
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Registered: ‎06-20-2011

Re: Icap fall-back detection. BOOTSTS

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Hi, I just noticed that Spartan-6 ICAP supports only 16-bit interface. So I modified my design to work with 16-bit data. Anyway,  the result was that icap returns IDCODE no matter what I write to icap input.

Please take a look my design, the results and input script. Should be attached.

 

Rgds,

Janne

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Observer
Observer
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Registered: ‎06-20-2011

Re: Icap fall-back detection. BOOTSTS

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Hi serge,

I forgot to mention that I use a custom board and my flash is ST M25P32. I shouldn't make any difference. I would be nice, if you could send me your script.

 

Janne

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4,993 Views
Registered: ‎06-29-2009

Re: Icap fall-back detection. BOOTSTS

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Hi, 

 

I have tried to find the demo I ever tested ... but I couldn't find it imediately (the project is already several months done ...  and I cant remember what is where)

 

BUT, now I remember:

 

I used the demo that is available in the xilinx directory.  It is actualy a demo for the microblaze , but you could get the appropriate code/sequence to use in your VHDL.  The demo is the result you see on top of these posts  (and as I remember STAT Reg is involved)

The demos can be found in C:\Xilinx\12.3\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\hwicap_v5_01_a\examples

or any other HWICAP demo in these directory.

(I think you realy need 12.3, since in older version there was no SPARTAN6 ICAP suported)

 

Hope this can fix ure isue, 

 

 

Grtz

 

 

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Observer
Observer
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Registered: ‎06-20-2011

Re: Icap fall-back detection. BOOTSTS

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Hi,

Thanks, I'll check that.

 

Janne

 

PS: Currently I use ISE 13.1

 

 

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Observer
Observer
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Registered: ‎06-20-2011

Re: Icap fall-back detection. BOOTSTS

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Hi serge,

I checked the icap control from hwicap sw examples and found a couple of small issues. I fixed those and now it works. Thanks for your help,

 

Rgds,

Janne

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Newbie
Newbie
4,123 Views
Registered: ‎06-10-2014

Re: Icap fall-back detection. BOOTSTS

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Hi eemeli;

Could you please mention about the issues you found? I am stuck in reading configuration registers too.

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