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Observer sanjaac
Observer
17,155 Views
Registered: ‎03-16-2009

Image from DDR to VGA - Spartan3E kit

Hello guys,

 

Following the discussion from the thread Spartan-3E, DDR, MIG , I want to share a project which enables to continuously show an image stored in DDR con the Spartan3E kit to VGA.

 

Some notes regarding this:

 

- Uses ISE10.1.3

- Uses DDR controller from MIG2.3

 

The purposes of this are:

 

- Have a framework for a project I am working on

- Test the DDR controller from MIG

- Help others to use easily the MIG-generated DDR controller on a S3E Kit.

 

The diagrams of it internals are published to:

 

www.sanjaac.com/pub/FPGA/MTC700_Camera_libvideo_streamerindex.htm

 

A test bench is published to:

 

www.sanjaac.com/pub/FPGA/MTC700_Camera_libvideo_streamer_tbindex.htm

 

 

Some notes about it:

 

- The access to the DDR controller is though block ddrctrl_arbitrer, which is the one that generates the waveforms needed for read, write and auto refresh as stated in UG086. The data movement is in blocks; the user simply loads the desired column, bank and row, and triggers a load_to_ddr signal. All the details on how to use it are within the block ctrl_controller which is within the block sys_ctrl.

- Block sys_ctrl controls the usage of the ddrctrl_arbitrer. It first triggers the in_stream, which will write an "image" into the DDR. When the whole image (800 x 600) is written, it then triggers the out_stream, which reads the contents of the DDR.

- Block in_stream simply writes block of data to the DDR thought the sys_ctrl and ddr_arbitrer blocks. The most important process into it is the so called "datagen"¨process. For this example we are generating a pattern which will be later interpreted as vertical strips of R - G - B, with an horizontal black stripe on line 512.

- Block out_stream is rather "complicated" in the details, although the philosophy is rather simple:

1. Read a line from the DDR and write it (buffer it) to BRAM. It runs at 100 MHz, full time spent on this is non predictable due to Auto Refresh cycles on the DDR and similar factors.

2. Read a buffered line from BRAM and send to the RGB generator (a decoder). It runs at VGA pixel clock, 50 Mhz in our case. Timing is very well defined and constant.

The BRAM is used as ping pong buffer. If reading from address 0x0000, then writting will be from address 0x0400. When each of these operations finishes, their "offsets" are toggled

- Block rgb_gen simply decodes the data buffered from BRAM into RGB values valid for the VGA "DAC" on the S3E kit.

 

Of course many ideas on interesting projects related to realtime image processing can arise from this small framework; first interesting idea/need is to replace the in_stream from a static one to a dynamic one, which accepts realtime video from a camera or CMOS sensor. Nevertheless important, hopefullly it will allow other designers use the DDR on an S3E kit much more easily in case that block transfers are acceptable or desired, just keep the block ddr_arbitrer. Indeed, given the fact that the waveforms for the DDR2 and DDR2 controllers from MIG are the same (according to UG086), this project can also be easily ported to the S3A or S3AN kits with only changing the DDR/DDR2 controller generated from MIG.

 

I will appreciate if many people can benefit from this work, and wil welcome all your feedback.

 

Kind regards.

18 Replies
Observer santiagordgz
Observer
17,086 Views
Registered: ‎11-01-2008

Re: Image from DDR to VGA - Spartan3E kit

Thaks so much for your contribution!

 

I've a project and by now the most tedious task has been the DDR controller, what I was trying to do is exactly what you did.

 

 

Message Edited by santiagordgz on 05-24-2009 08:58 AM
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Explorer
Explorer
17,008 Views
Registered: ‎02-18-2008

Re: Image from DDR to VGA - Spartan3E kit

Hi sanjaac,

 

I found your work very interesting and usefull, but I have some troubles to modifie your code to my porpouses

 

Could you help me? 

 

I wish to understand how code works splitting the write,read phase into different modules.

 

I have done the simplest part: ddr inititialization...

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Observer sanjaac
Observer
16,989 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Hello Alex,

 

I hope you first tried it on the S3E Kit out of the box, and that it worked.

 

I woud like to explain it very carefully, but it would take looooonnnnnnngggggg post, and be tooo boring. So, if you have specific questions, I would be more glad to answer them. As documentation you have the whole VHDL code and the provided link, besides whole test bench. Combined, they are very useful to understand how those things work.

 

Of course you canmodify your code to make it simulate faster, like for example writting and reading only, say, 5 rows, instead of 600. Or modify the state machine in sys_ctrl to go directly to read -once you have understood the writes- instead of having to wait for so long.

 

Regards.

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Explorer
Explorer
16,972 Views
Registered: ‎02-18-2008

Re: Image from DDR to VGA - Spartan3E kit

Hi Sanjaac,

 

you're right...your code works correctly.

 

Now probably it's a stupid problem: I create a new project adding the ddr controller and ddr.v and ddr_parameters.vh.

 

I make following your code the "write" process but when I try to sim there is an error because the ddr.v has the lenght of address egual to 14 and my (as your 13)...

 

my suspect is that I don't define a macro because in the .vh there are a lot of ifdef: I don't find any place in which you define "x128" or "x16"

 

how can I define it?

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Observer sanjaac
Observer
16,956 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Hi,

Which simulaor are you using? I used Modelsim, and remember some warning about mismatch between some definitions regarding the ddr.v at start up, but really did not pay attention to it, and it ran just fine.

You can have a look at the .vh file included, which has the parameters for the ddr.v model.

Do not hesitate to contact me if I can be of further help.

Regards.
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Explorer
Explorer
16,924 Views
Registered: ‎02-18-2008

Re: Image from DDR to VGA - Spartan3E kit

Hi Sanjaac,

 

 I try to sim the ddr core with ddr.v but it seems not working:

 

1) I dont' see any message in Modelsim console after initialization

2) not response when I send a command

3) no autorefresh...

 

I add the ISE 10.1 project and the "do" file could you see  where is the problem?

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Observer sanjaac
Observer
16,898 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Alex,

 

I tried, but also do not see it coming out, many signals remain in undefined states (red). Check that out!

 

First thing, did you study the reset structure? In my code, the reset depends both on the external reset and the DCM locking; besides tha, around a c certain time (350 us - 380 u) the system fully initializes.

 

Please try to simulate the both ISE projects that I have uploaded in order to get an idea of how it works; they do run fully and prefectly.When the DDR is up and running you get something like this:

 

# At time 333110.000 ns LMR  : Burst Length = 4
# At time 333110.000 ns LMR  : CAS Latency = 2
# At time 334110.000 ns LMR  : Burst Length = 4
# At time 334110.000 ns LMR  : CAS Latency = 2
# ** Note: INITIALIZATION_DONE

 

 

Also, in the file ddr_parameters.vh if you can change the last line to:

 

parameter DEBUG            =       1; // Turn on DEBUG message 

 

You will get a long file "trancsript", which has information like this, more or less (from my original DDR tester in the other post on the Forum):

 

# At time 332610.000 ns PRE  : Addr[10] = 1, Bank = 00
# At time 332860.000 ns EMR  : Extended Mode Register
# At time 332860.000 ns EMR  : Enable DLL
# At time 333110.000 ns LMR  : Load Mode Register
# At time 333110.000 ns LMR  : Burst Length = 4
# At time 333110.000 ns LMR  : CAS Latency = 2
# At time 333360.000 ns PRE  : Addr[10] = 1, Bank = 00
# At time 333610.000 ns AREF : Auto Refresh
# At time 333860.000 ns AREF : Auto Refresh
# ddrctrl_tester_tb.u_2: at time 333860.000 ns MEMORY:  Power Up and Initialization Sequence is complete
# At time 334110.000 ns LMR  : Load Mode Register
# At time 334110.000 ns LMR  : Burst Length = 4
# At time 334110.000 ns LMR  : CAS Latency = 2
# ** Note: INITIALIZATION_DONE
#    Time: 335105 ns  Iteration: 3  Instance: /ddrctrl_tester_tb/u_0/u_4/top_00/controller0
# At time 335180.000 ns ACT  : Bank = 0, Row = 0000
# At time 335210.000 ns WRITE: Bank = 0, Col = 000
# At time 335225.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 0000
# At time 335230.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 0001
# At time 335230.000 ns WRITE: Bank = 0, Col = 004
# At time 335235.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 0002
# At time 335240.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 0003
# At time 335245.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 0004
# At time 335250.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 0005
# At time 335250.000 ns WRITE: Bank = 0, Col = 008
# At time 335255.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 0006
# At time 335260.000 ns WRITE: Bank = 0, Row = 0000, Col = 007, Data = 0007
# At time 335265.000 ns WRITE: Bank = 0, Row = 0000, Col = 008, Data = 0008
# At time 335270.000 ns WRITE: Bank = 0, Row = 0000, Col = 009, Data = 0009

...

etc, etc.

...

# At time 436025.000 ns READ : Bank = 0, Row = 0008, Col = 3fb, Data = 23fb
# At time 436030.000 ns READ : Bank = 0, Row = 0008, Col = 3fc, Data = 23fc
# At time 436035.000 ns READ : Bank = 0, Row = 0008, Col = 3fd, Data = 23fd
# At time 436040.000 ns READ : Bank = 0, Row = 0008, Col = 3fe, Data = 23fe
# At time 436045.000 ns READ : Bank = 0, Row = 0008, Col = 3ff, Data = 23ff
# At time 436050.000 ns PRE  : Addr[10] = 1, Bank = 00
# At time 437780.000 ns AREF : Auto Refresh
# At time 448040.000 ns AREF : Auto Refresh
# At time 458300.000 ns AREF : Auto Refresh
# At time 468560.000 ns AREF : Auto Refresh
# At time 478820.000 ns AREF : Auto Refresh
# At time 489080.000 ns AREF : Auto Refresh
# At time 499340.000 ns AREF : Auto Refresh
# At time 509600.000 ns AREF : Auto Refresh
# At time 519860.000 ns AREF : Auto Refresh
# At time 530120.000 ns AREF : Auto Refresh
# At time 540380.000 ns AREF : Auto Refresh

 

A screenshot of the simulation waveforms for this project is attached.

 

So, my advice:

 

- Start with the  already working simulations.

- Move slowly, changing ONLY what you need, take my work as a base to do your upper level stuff.

- Then change in a lower level what you need.

 

Regards ,

ddr_test_1.png
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Observer sanjaac
Observer
16,897 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Also, here I am atatching a simulation waveform of the DDR+VGA project. As you can see, it is less than 1 ms and has only the write to DDR sequence illustrated; after a long simulation time (time that I do not have now) it will show the read waveforms working perfectly. As said, take that as a foundation from the top down, that is my advice.

 

Good luck,

ddr_test_2.png
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Explorer
Explorer
16,713 Views
Registered: ‎02-18-2008

Re: Image from DDR to VGA - Spartan3E kit

Hi Sanjaac,

 

could you explain me what I see (also you) during the simulation of ddr core?

 

#    Time: 335105 ns  Iteration: 3  Instance: /video_streamer_tb/i0/u_4/top_00/controller0
# At time 335200.000 ns ACT  : Bank = 0, Row = 0000
# At time 335230.000 ns WRITE: Bank = 0, Col = 000
# At time 335245.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 7c00
# At time 335250.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 7c00


# At time 335250.000 ns WRITE: Bank = 0, Col = 004
# At time 335255.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 7c00
# At time 335260.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 7c00
# At time 335265.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 7c00
# At time 335270.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 7c00


# At time 335270.000 ns WRITE: Bank = 0, Col = 008
# At time 335275.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 7c00

 

Why the first write cmd has 2 col addres and the second (004) four?

 

I'm a little confused...

 

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Historian
Historian
10,160 Views
Registered: ‎02-25-2008

Re: Image from DDR to VGA - Spartan3E kit


alexgiul wrote:

Hi Sanjaac,

 

could you explain me what I see (also you) during the simulation of ddr core?

 

#    Time: 335105 ns  Iteration: 3  Instance: /video_streamer_tb/i0/u_4/top_00/controller0
# At time 335200.000 ns ACT  : Bank = 0, Row = 0000
# At time 335230.000 ns WRITE: Bank = 0, Col = 000
# At time 335245.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 7c00
# At time 335250.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 7c00


# At time 335250.000 ns WRITE: Bank = 0, Col = 004
# At time 335255.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 7c00
# At time 335260.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 7c00
# At time 335265.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 7c00
# At time 335270.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 7c00


# At time 335270.000 ns WRITE: Bank = 0, Col = 008
# At time 335275.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 7c00

 

Why the first write cmd has 2 col addres and the second (004) four?

 

I'm a little confused...

 


Looks like his test bench is simply doing a burst of two writes, followed by a burst of four. There is nothing particularly odd about this.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Observer sanjaac
Observer
10,159 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Hi bassman59, Alex.

 

As bassman said, there is nothing special into it. You can just continue working with the code and core.

 

Good luck.

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Explorer
Explorer
10,149 Views
Registered: ‎02-18-2008

Re: Image from DDR to VGA - Spartan3E kit

Hi bassman59, Sanjaac,

 

probably I post the question in uncorrect manner: I write code to obtain the waveforms of figure 7-9 page 254 of ug086.pdf.

 

In the note of figure, it's written:  DDR SDRAM Write Burst, Burst Lengths of Four and Two Bursts , so why the first write is 2 burst and second and other no?

 

According to the above figure, I have to increment the column counter , now I add 4 every iteration to column counter, but I'm not sure if it's right

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Observer sanjaac
Observer
10,138 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Hi guys,

 

I will re-copy here were the ACTUAL writes are, for you to see it very clearly:

 

# At time 335245.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 7c00
# At time 335250.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 7c00

# At time 335255.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 7c00
# At time 335260.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 7c00
# At time 335265.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 7c00
# At time 335270.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 7c00

# At time 335275.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 7c00

 

Can't you see now that it is working prefectly:

 

- A write every 5 ns (2x 100 MHz)

- We are in the same row

- The columns are incrementing linearly as expected

- No jumps

- No misses

- Everything working just smoothly.

 

Hopefuly all your confusion is gone now.

 

Regards,

 

JaaC

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Visitor nhungth
Visitor
8,929 Views
Registered: ‎04-19-2010

Re: Image from DDR to VGA - Spartan3E kit

Hi Sanjaac,

 

At the moment, I am the last-year student and I have to work with FPGA in my thesis. Can you help me how to use EDK 10.1 to control DDR-SDRAM? I am using Spartan 3E Starter Kit.

 

I am looking forward to hearing from you.

 

Best Regards,

 

Nhung.

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Observer sanjaac
Observer
8,922 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Hi,

 

Well, the easy answer is: generate it on MIG (LogiCore), and build a controller for it according to the specs in the User Manual/Datasheet; there is where the fun is!

 

If you have more specific questions like those posted on the forum -did you read them already? did you try to dot it yourself already?-, maybe I could help. But I can not do your last year thesis.

 

Regards,

 

JaaC

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Visitor nhungth
Visitor
8,919 Views
Registered: ‎04-19-2010

Re: Image from DDR to VGA - Spartan3E kit

Hi Sanjaac,

 

Thank you for replying me!

 

Actually, I have already read some  related questions on this forum as well as other websites but everything seems too hard for a new person about FPGA like me. I also read the Datasheet but it is too long and I do not know where I can start. However, I will try to understand something in it and do the thesis myself.

 

One more thing, I never want to depend on another person in my work.

 

I am sorry if that is a silly question!

 

Best Regards,

 

Nhung.

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Visitor deepa
Visitor
8,076 Views
Registered: ‎05-04-2009

Re: Image from DDR to VGA - Spartan3E kit

Hi

 

I came across your post when I was looking for VGA controller code for Spartan 3E. I just want to know if we can create more than the available 8 colors in S3E? I see that we are using only 5 pins. Are more colors possible? Please let me know.

 

Thanks

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Observer sanjaac
Observer
8,057 Views
Registered: ‎03-16-2009

Re: Image from DDR to VGA - Spartan3E kit

Hi deepa,

 

Sure it is possible, with some HW rework. I have not done it, and -unfortunately- at this moment have no time to go look the schematics and figure out how to do it. Probably you are able to do it yourself, good luck and have fun!

 

JaaC

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