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Visitor maierhc
Visitor
5,070 Views
Registered: ‎06-24-2008

Inference of DSP48A1 in Spartan 6 Devices

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Hello,

 

I already know, that it's possible to instantiate the DSP48A1 Blocks via Language Templates or the IP-Core Generator.

Xilinx User Manual of the DSP48A1 Slices (www.xilinx.com/support/documentation/user_guides/ug389.pdf) although says, that there is also a way to infer these Slices only using standard VHDL without any Primitives.

 

Is there an existing VHDL discription of this block ?

 

 

Thanks in advance

chris

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Xilinx Employee
Xilinx Employee
5,924 Views
Registered: ‎11-28-2007

Re: Inference of DSP48A1 in Spartan 6 Devices

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You can get DSP48 inferenece examples from the link below:

 

ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip

Cheers,
Jim

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Xilinx Employee
Xilinx Employee
5,925 Views
Registered: ‎11-28-2007

Re: Inference of DSP48A1 in Spartan 6 Devices

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You can get DSP48 inferenece examples from the link below:

 

ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip

Cheers,
Jim

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Visitor ccgccg
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3,660 Views
Registered: ‎02-20-2012

Re: Inference of DSP48A1 in Spartan 6 Devices

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Is it possible to write VHDL that will cause XST to infer DSP48A1 with an asynchronous reset output register?

i.e. VHDL equivalent to instantiating with the RSTTYPE attribute set to ASYNC

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