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Observer boy_fpga
Observer
7,707 Views
Registered: ‎10-01-2011

Interfacing Spartan 6 Atlys board with DDR memory without EDK

Hello,
has anyone managed to interface Atlys with DDR memory without using the (expensive) EDK?
I downloaded the example from tristesse's site http://tristesse.org/FPGA/XilinxMIGTutorial,
but couldn't really get how the things are working...
What I need is the ability of storing some data in the ddr memory and then reading from it.
is there some working example anywhere? Or alternatively, could anyone point me in the right direction?

Thank you

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9 Replies
Scholar joelby
Scholar
7,705 Views
Registered: ‎10-05-2010

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

What were the problems you had with my example code?

Visitor david.dhas1
Visitor
7,546 Views
Registered: ‎10-08-2012

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

I have a Spartan 6 SP601 board . I need to design a counter that can store upto 100 numbers in the DDR 2 RAM and print them back . Could you help me with the memory interface after the creation of the MIG .

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Scholar joelby
Scholar
7,541 Views
Registered: ‎10-05-2010

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

It'll be better to open a new thread than to append your issue to this one.

 

When you do, please tell us what you've managed to do so far and what isn't working.

 

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Visitor david.dhas1
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7,537 Views
Registered: ‎10-08-2012

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

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Visitor hassaniqbal
Visitor
3,429 Views
Registered: ‎08-12-2016

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

Hello @joelby

 

I have added my logic into your code and downloaded it to my Atlys (actually integrated your code into XAPP495 for external memory interface). The output is blank as if its not reading or writing or not doing both to DDR2. I have outputted c3_clk0 signal for debugging purposes from my Atlys but the signal is only low voltage noise (no clock). Please guide how should I go about in solving this issue.

 

Thank you.  

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Visitor hassaniqbal
Visitor
3,426 Views
Registered: ‎08-12-2016

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

Also please note that my Atlys has MIRA P3R1GE3EGF G8E DDR2 component, so I have updated your IP core by selecting "EDE1116AXXX-8E" device as recommended in Atlys™ FPGA Board Reference Manual. I have kept the value of reset as '0' all the time. 

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Scholar joelby
Scholar
3,408 Views
Registered: ‎10-05-2010

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

If the design is completely failing to do something you would expect, such as outputting a clock to a pin, the first thing I would check is the output of your synthesis results. Is the tool discarding/trimming most of your design because of a typo or something like that?

 

 

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Visitor hassaniqbal
Visitor
3,402 Views
Registered: ‎08-12-2016

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

In the design summary text report of synthesis, there are numerous warnings. I have found these warnings which may require some attention. I have attached the synthesis report. Please guide how to resolve this issue. Thank you.

 

WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 865: Net <mig_p1_cmd_clk> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 866: Net <mig_p1_cmd_en> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 867: Net <mig_p1_cmd_ra[14]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 868: Net <mig_p1_cmd_ba[2]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 869: Net <mig_p1_cmd_ca[11]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 871: Net <mig_p1_cmd_instr[2]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 872: Net <mig_p1_cmd_bl[5]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 896: Net <mig_p3_cmd_bl[5]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 945: Net <mig_p2_wr_data[31]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 947: Net <mig_p4_wr_data[31]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 953: Net <mig_p2_wr_mask[3]> does not have a driver.
WARNING:HDLCompiler:634 - "F:\Projects\MultiVision\atlys_ddr_test - Copy\ipcore_dir\ddr2\user_design\rtl\mcb_controller\mcb_raw_wrapper.v" Line 955: Net <mig_p4_wr_mask[3]> does not have a driver.

 

 

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Scholar joelby
Scholar
3,394 Views
Registered: ‎10-05-2010

Re: Interfacing Spartan 6 Atlys board with DDR memory without EDK

I've had a look and unfortunately I can't see anything obvious, sorry. The MIG and the XAPP495 are a little "noisy" in that they provide some extra ports and stuff that you might not actually use, so things are bound to get trimmed anyway.

All I can suggest is a few basic design principles:

- Make sure you always use `default_nettype none to ensure that typos lead to synthesis errors rather than bizarre issues
- Make sure the basic design works (e.g. just the XAPP495 part) before adding new bits on
- Use test benches to verify the design. It can be a bit tricky to simulate complicated things like MIG designs (which is not really feasible to simulate with the free version of ISim), but otherwise very worthwhile
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