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Visitor palvarez
Visitor
7,040 Views
Registered: ‎11-24-2009

Interfacing a clipped sine wave TCXO with Spartan6

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Hi Everybody,

 

Does anyone know of a simple, nice and clean way of interfacing a standard clipped sine wave oscillator to an Spartan6?

 

Thanks for your help

 

Pablo 

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1 Solution

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Scholar austin
Scholar
8,636 Views
Registered: ‎02-27-2008

Re: Interfacing a clipped sine wave TCXO with Spartan6

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Pablo,


I do not know (if it will drive the input, through a 50 ohm pcb trace).  Try it.  Measure it with a 'scope.

 

If the singal is centered around ground (going both + and -), you will have to capacitively cuople it, and bias it to 1/2 Vcco of the IO bank before applying it to an input.   Split 100K resistors, one to Vcco, one to ground, willbias the input to mid-range.  Vref is then set to 1/2 Vcco from a simialr split resistor network, with a decoupling capacitor to ground on each Vref pins all connected together for the bank (even though you use only one input).


No, I do not suggest termining the signal (the sinewave clock does not need a termination).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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5 Replies
Scholar austin
Scholar
7,031 Views
Registered: ‎02-27-2008

Re: Interfacing a clipped sine wave TCXO with Spartan6

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Pablo,

 

Use the SSTL or HSTL input with a Vref set at 1/2 the signal.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor palvarez
Visitor
7,023 Views
Registered: ‎11-24-2009

Re: Interfacing a clipped sine wave TCXO with Spartan6

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Thanks for the quick answer Austin!

 

I was thinking of that, but in standard TCXOs clipped sinewave outputs are normally specified as "10k // 10pF, Decoupled". Do you think it can drive the 50Ohm SSTL termination?

 

Pablo 

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Visitor palvarez
Visitor
7,020 Views
Registered: ‎11-24-2009

Re: Interfacing a clipped sine wave TCXO with Spartan6

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Hi Austin,

 

I guess you propose not to use the internal OPTIONAL termination.

 

Thanks in any case for the help

 

pablo  

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Scholar austin
Scholar
8,637 Views
Registered: ‎02-27-2008

Re: Interfacing a clipped sine wave TCXO with Spartan6

Jump to solution

Pablo,


I do not know (if it will drive the input, through a 50 ohm pcb trace).  Try it.  Measure it with a 'scope.

 

If the singal is centered around ground (going both + and -), you will have to capacitively cuople it, and bias it to 1/2 Vcco of the IO bank before applying it to an input.   Split 100K resistors, one to Vcco, one to ground, willbias the input to mid-range.  Vref is then set to 1/2 Vcco from a simialr split resistor network, with a decoupling capacitor to ground on each Vref pins all connected together for the bank (even though you use only one input).


No, I do not suggest termining the signal (the sinewave clock does not need a termination).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor palvarez
Visitor
7,015 Views
Registered: ‎11-24-2009

Re: Interfacing a clipped sine wave TCXO with Spartan6

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Now everything is clear. 

 

Thanks again for the recipe ;)

 

pablo 

 

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