We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor tvlad
Registered: ‎10-16-2008

Internal pull-up resistors issue in JTAG mode


My HW design supports two FPGA configuration modes: Master SPI mode and JTAG mode. I need to keep I/O user pins in the High level state during configuration. I activate the internal pull-up resistors with connecting HSWAP pin to ground through 330Ω resistor. It works in the Mater SPI mode (M<0:0:1>) but in the JTAG mode (M<1:0:1>) all I/O user pins go to logical zero immediately with INIT_B goes to logical one. How can I resolve this issue?  


Baground information:

1. Device Spartan3E (XA3S500E).

2. Power supply Vcco=3.3V, Vccaux=2.5V, Vccint=1.2V

3. Vccaux and Vccint are derived from Vcco.

4. All mode pins (M0, M1, M2) connect to GND or Vccaux through 330Om resistors.

5. HSWAP pin connects to GND through 330Ω resistor.

6. INIT_B pin connects to Vcco through 4k7 resistor.

7. PROG_B and DONE have external pull-up 4k7 resistors that connect to Vccaux.


Thanks in advance.

0 Kudos