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Visitor richardjones
Visitor
5,138 Views
Registered: ‎08-10-2010

LOC: component names for GENERATEd logic

I've a block of BRAMs created in a GENERATE FOR loop (VHDL) for a Spartan-6 that end up with lousy placements, they're scattered here and there. I'd like to LOC them somewhere sensible, close to some DSP48 slices I've just LOD'd to reduce the associated routing delays and gain me some slack.

 

bram_gen : for n in 0 to 11 generate

 sram : RAMB16BWER

 generic map (...)

 port map (...)

 

I've hit a problem, their names are on the lines of  "A/B/C/bram_gen[0].sram" which as you can see contains square braces and a dot.

 

I've been dropping my LOC sttributes into my VHDL source code for now, they'll migrate to my UCF in due course. This means I'd like to write the following in VHDL:

 

attribute LOC : string;

attribute LOC of bram_gen[0].sram : label is "RAMB16_X0Y0";

attribute LOC of bram_gen[1].sram : label is "RAMB16_X0Y2";

 

These are invalid: "Syntax error near "0"". Trying different permutations didn't get me anywhere, does anyone have any ideas, other than instantiate tham long-hand.

 

 

 

 

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6 Replies
Xilinx Employee
Xilinx Employee
5,117 Views
Registered: ‎11-28-2007

Re: LOC: component names for GENERATEd logic

You need to add attribute inside the generate statement and also generate the value for the label on the fly.

 

 


@richardjones wrote:

I've a block of BRAMs created in a GENERATE FOR loop (VHDL) for a Spartan-6 that end up with lousy placements, they're scattered here and there. I'd like to LOC them somewhere sensible, close to some DSP48 slices I've just LOD'd to reduce the associated routing delays and gain me some slack.

 

bram_gen : for n in 0 to 11 generate

 sram : RAMB16BWER

 generic map (...)

 port map (...)

 

I've hit a problem, their names are on the lines of  "A/B/C/bram_gen[0].sram" which as you can see contains square braces and a dot.

 

I've been dropping my LOC sttributes into my VHDL source code for now, they'll migrate to my UCF in due course. This means I'd like to write the following in VHDL:

 

attribute LOC : string;

attribute LOC of bram_gen[0].sram : label is "RAMB16_X0Y0";

attribute LOC of bram_gen[1].sram : label is "RAMB16_X0Y2";

 

These are invalid: "Syntax error near "0"". Trying different permutations didn't get me anywhere, does anyone have any ideas, other than instantiate tham long-hand.

 

 

 

 


 

Cheers,
Jim
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Visitor richardjones
Visitor
5,088 Views
Registered: ‎08-10-2010

Re: LOC: component names for GENERATEd logic

Thanks Jim, I'd not realized I could label each instance in the generate loop as I wish, I presume it's just a case of constructing a concatenation of characters into a string.

 

Won't I still get an instance name something like "A/B/C/bram_gen[0].sram0", "A/B/C/bram_gen[0].sram1" and so on, the square braces and dot preceeding any locally created label "sram" & n?

 

 

 

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Xilinx Employee
Xilinx Employee
5,063 Views
Registered: ‎11-28-2007

Re: LOC: component names for GENERATEd logic

Yes, you will still get the same instance names. The synthesis tools will take care of attaching correct attribute values to the corresponding instances when you place the attribute inside "generate" statement.

 


@richardjones wrote:

Thanks Jim, I'd not realized I could label each instance in the generate loop as I wish, I presume it's just a case of constructing a concatenation of characters into a string.

 

Won't I still get an instance name something like "A/B/C/bram_gen[0].sram0", "A/B/C/bram_gen[0].sram1" and so on, the square braces and dot preceeding any locally created label "sram" & n?

 

 

 


 

Cheers,
Jim
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Visitor diplomat
Visitor
4,826 Views
Registered: ‎07-15-2010

Re: LOC: component names for GENERATEd logic

But if I do this:

 

 

gen_ramb16_s1_s36 : for i in 0 to 31 generate
attribute DATA_WIDTH_A : integer; --
      attribute DATA_WIDTH_A of gen_ramb16_s1_s36[i].RAMB16BWE_S36_inst : label is 9;


[...]

begin
RAMB16BWE_S36_inst : RAMB16BWE_S36
generic map (
INIT => X"000000000", -- Value of output RAM registers at startup

port map (
DO => DO_RAM, -- 32-bit Data Output
DOP => open, -- 4-bit parity Output
ADDR => ADDR_RAM, -- 9-bit Address Input

[...]
end generate;

 

ISE will still throw out some errors... what am I doing wrong????

 

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Teacher eteam00
Teacher
4,817 Views
Registered: ‎07-21-2009

Re: LOC: component names for GENERATEd logic

diplomat:

 

You should start a new thread, as this is a new topic.

You should post the error messages, they include valuable information.

 

-- Bob Elkind

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Highlighted
Adventurer
Adventurer
2,311 Views
Registered: ‎01-09-2014

Re: LOC: component names for GENERATEd logic

Old thread but still a hit while doing search on google.

In Vivado for a similar thing (IODelay & IDDR in my case) I had to:

 

 

pin_delay_gen : for pin in 0 to SYS_W_G -1 generate
	
	attribute IODELAY_GROUP : STRING;
	attribute IODELAY_GROUP of IDELAYE2_dat_inst	: label is "RGMII_IDDR_group";
	
begin

	IDELAYE2_dat_inst : IDELAYE2
	generic map (		
		CINVCTRL_SEL			=>	"FALSE",								-- Enable dynamic clock inversion (FALSE, TRUE)
		DELAY_src=>	"IDATAIN",								-- Delay input (IDATAIN, DATAIN)
		HIGH_PERFORMANCE_MODE	=>	"FALSE",								-- Reduced jitter ("TRUE"), Reduced power ("FALSE")
		IDELAY_TYPE				=>	"FIXED",								-- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
		IDELAY_VALUE			=>	DATA_TAP_G(pin),					-- Input delay tap setting (0-31)
		REFCLK_FREQUENCY		=>	200.0,									-- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
		PIPE_SEL				=>	"FALSE",								-- Select pipelined mode, FALSE, TRUE
		SIGNAL_PATTERN			=>	"DATA"									-- DATA, CLOCK input signal
	)
	port map (
		DATAOUT					=>	data_in_from_pins_delay(pin),		-- 1-bit output: Delayed data output
		DATAIN					=>	'0',									-- 1-bit input: Internal delay data input
		C						=>	'0',									-- 1-bit input: Clock input
		CE						=>	'0',									-- 1-bit input: Active high enable increment/decrement input
		INC						=>	'0',									-- 1-bit input: Increment / Decrement tap delay input
		IDATAIN					=>	data_in_from_pins_int(pin),		-- 1-bit input: Data input from the I/O
		LD						=>	'0',									-- 1-bit input: Load IDELAY_VALUE input
		REGRST					=>	'0',									-- 1-bit input: Active-high reset tap-delay input
		LDPIPEEN				=>	'0',									-- 1-bit input: Enable PIPELINE register to load data input
		CNTVALUEIN				=>	"00000",								-- 5-bit input: Counter value input
		-- CNTVALUEOUT				=>	open,									-- 5-bit output: Counter value output
		CINVCTRL				=>	'0'										-- 1-bit input: Dynamic clock inversion input
	);
end generate pin_delay_gen;

 

otherwise when I used:

pin_delay_gen[pin].IDELAYE2_dat_inst

I had an error:

 

 

[HDL 9-806] Syntax error near "."

 

TJ

 

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