cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sha@hys
Explorer
Explorer
11,624 Views
Registered: ‎05-31-2015

LVCMOS33 voltage levels

Jump to solution

Hello,

 

                  I have driven 3 pins of my FPGA to 1,0 and a clock respectively and get voltage levels of 3.3 ,0 and 5.2V(peak to peak) when I view waveform in analog mode in oscilloscope. I expect clock to be having 3.3V peak to peak. My clock is output from clock generator , given to ODDR2 to eliminate clock dedicated route false problem . In UCF file I have explicitly mentioned clock pin and other pins to be LVCMOS33 standard. Please explain why is this so? I want 3.3Vpp clock to drive DAC board. My code sgments are:

 

clockinstance_1 : clkgen
port map
(-- Clock in ports
CLK_IN1 =>CLK,
-- Clock out ports
CLK_OUT1 => open,
CLK_OUT2 => clk_25,
CLK_OUT3 => clk_12,
-- Status and control signals
LOCKED => LOCKED);

 

 

oddrinst:ODDR2 PORT map(
D0=>'1',
D1=>'0',
C0=>clk_12,
C1=>not(clk_12),
Q=>clk4DAC
);

 

With Regards

Shalini

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
chapman
Xilinx Employee
Xilinx Employee
21,369 Views
Registered: ‎09-05-2007

My guess is that your ‘clk_25’ signal looks more like a sinusoidal waveform than a square wave. If so, what you are observing is the overshoot and undershoot of every transition.

 

For an experiment, try dividing your clock with a counter and outputting a lower frequency square wave (e.g. <2MHz). Then I expect you will see that you do have a more square looking waveform which generally switches between 0v and 3.3v. Then look closely at each transition and see how much the signal overshoots or undershoots and for how long.

 

This is why outputs can be defined to have different slew rates and drive strengths and why correct termination of clock (and other critical) signals on circuit boards becomes such an important subject.

Ken Chapman
Principal Engineer, Xilinx UK

View solution in original post

0 Kudos
4 Replies
logison
Observer
Observer
11,608 Views
Registered: ‎03-05-2013

Check your supply voltage on Vcco pins. I'm affraid you don't have 3.3V on that pins but 5V instead.

0 Kudos
sha@hys
Explorer
Explorer
11,605 Views
Registered: ‎05-31-2015

hello,

   

   No my VCCO is 3.3V only,not 5 V. Also when I drive 1 from VHDL program to pin in same bank , I get the same 3.3V only.

0 Kudos
chapman
Xilinx Employee
Xilinx Employee
21,370 Views
Registered: ‎09-05-2007

My guess is that your ‘clk_25’ signal looks more like a sinusoidal waveform than a square wave. If so, what you are observing is the overshoot and undershoot of every transition.

 

For an experiment, try dividing your clock with a counter and outputting a lower frequency square wave (e.g. <2MHz). Then I expect you will see that you do have a more square looking waveform which generally switches between 0v and 3.3v. Then look closely at each transition and see how much the signal overshoots or undershoots and for how long.

 

This is why outputs can be defined to have different slew rates and drive strengths and why correct termination of clock (and other critical) signals on circuit boards becomes such an important subject.

Ken Chapman
Principal Engineer, Xilinx UK

View solution in original post

0 Kudos
sha@hys
Explorer
Explorer
11,465 Views
Registered: ‎05-31-2015

Hello,

 

Thank you for reply. You are correct.

 

With Regards

shalini

0 Kudos