UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor zxliying
Visitor
7,131 Views
Registered: ‎01-05-2016

LVDS problem when using ISERDES module, according to XAPP1064

Hi,

  I'm using XC6SLX45-2CSG324 to acquire TI AFE5803's LVDS data. The timing diagrams adn LVDS module are shown in the attachments. The sampling frequency is 50MHz and the adc reselotion is 14bits. So the Frame clock is 50MHz and the bit clock is 350MHz. Reference design files from the XAPP1064 are used as the LVDS module including serdes_1_to_n_clk_pll_s16_diff.v,serdes_1_to_n_data_s16_diff.v and top_nto1_pll_diff_rx.v. The Frame clock is sampled as a frame signal which is used to align the data. So the Deserialized frame signal should be 14'h007F or shifted a little bits.  Here comes the problem, the Deserialized frame signal are not always 7 '0's and 7 '1's. It can be 14'h078F, 14'h3F7E, 14'h0000, 14'h3C78, 14'h0183, 14'h3060, 14'h1FBF. I tried to reset the LVDS module and the right pattern and wrong pattern are randomly come out. After each reset the pattern always stay the same no matter right or wrong pattern. Can anybody help me solve this problem?

timing.jpg
0 Kudos