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Visitor oszillator
Visitor
9,773 Views
Registered: ‎07-18-2011

Limitations of XAPP945 on the Atlys Board

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Hello,

iam currently working with the XAPP945 DVI-Matrix on the Atlys Development Board. Everything looks very fine, but i am wondering why it is possible to route videos at a pixel clock of 147 MHz with a resolution of 1680x1050x32b-60Hz error-free.

 

To my understanding, the maximal throughput is limited to 945 Mbit/s per TMDS channel, and since 10 bits per clock are transmitted (2b/4b/8b to 10b encoding), the maximum possible pixel clock should be at 94,5 MHz.

 

Where did i go wrong?

 

Thanks in advance

oszi

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Teacher eteam00
Teacher
12,325 Views
Registered: ‎07-21-2009

UPDATED: Understanding DVI/HDMI and Atlys, part 2

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XAPP 495 does not support HDMI due to the missing encoder/decoder

 

This is news to me!  HDMI is primarily a physical transport layer standard, with certain requirements for video format support.  Additional video formats may be supported, but such support is optional.

 

I think your imprecise use of words may mislead to unsupported conclusions.

 

imho, it is vice versa, the audio codec is chosen by the blanking interval duration such that it fits. I added my resolution to your table:           

width      height    rate    width   height   pixel clock
1650        1080     60     2256     1087      147,14

 

The audio codec is chosen by the audio source, not the interface physical transport layer, based on sample rate and bits/sample and data encoding.  Perhaps your definition of 'audio codec' differs from mine.

 

In any case, pixel rates which exceed the datasheet specifications for either Spartan-6 or TI TMDS141 may indeed work (and often do work) -- but they are not guaranteed to work.

 

According to table 2 of  Xapp495 Doc, the throughput directly corresponds to the pixel clock. Hence, a 147.14 MHz clock results in a throughput of 1.47 Gbit/s, thats still about 400 Mbit/s more than speed grade -3 should allow.

 

Correct on all points.

 

Even SXGA with a pixel clock of 108 MHz should not work, but it does!

 

1080Mb/sec (108MHz pixel clock) matches the upper limit datasheet spec for -3 speed grade Spartan-6 devices.

 

Maybe there is a mistake on that table? Or do we miss something else?

 

No mistake in the table whatsoever.  The table is for informational puposes.  I point you to the paragraph following Table 2:

 

For the first time, the most popular 720p and 1080i resolution is achievable in most Spartan-6 devices (except the -1L speed grade).

 

I do not detect any representation that Spartan-6  supports any DVI/HDMI video format which exceeds the Spartan-6 datasheet guarantees.

 

-- Bob Elkind

SIGNATURE:
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View solution in original post

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Spartan-6 serial bitrate limits, Atlys design

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Refer to S-6 datasheet DS162, Table 25.  For Spartan-6 devices, maximum ISERDES2 or OSERDES2 bit rate is

  • 1080 Mbits/sec (-3 speed grade)
  • 1050 Mbits/sec (-3N speed grade)
  • 950 Mbits/sec (-2 speed grade)

I haven't examined XAPP945 XAPP495 to discern bandwidth relationship (if any) between individual input/output video streams (in the I/O section) and word (pixel) routing/switching in the fabric of the FPGA.  It stands to reason that the fabric logic clock frequency  is *not* tied to the pixel rate clock for any single input/output video stream, particularly for a design which supports multiple input and output video streams.

 

A decoupled (independent) fabric clock provides the simplest explanation for "why it is possible to route videos at a pixel clock of 147 MHz with a resolution of 1680x1050x32b-60Hz error-free".

 

I am not an Atlys board user/owner.  Perhaps user joelby will shed additional light on this subject.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Scholar joelby
Scholar
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Registered: ‎10-05-2010

Re: Spartan-6 serial bitrate limits, Atlys design

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I don't actually know much about HDMI, but isn't the pixel clock just W*H*Refresh = 1680 * 1050 * 60 = 105.84 MHz? Where did you get the 147 MHz figure from?

 

There is a raging debate going on about the speed grade of the chip on that Atlys. It could be either -2 or -3 but until someone cracks the heatsink off, we can't be sure. Bear in mind that a part marked -2 might work fine at -3 speeds under good conditions - just like Digilent, the FPGA doesn't actually know what speed grade it is. It doesn't detect higher SERDES speeds than its rated for and switch off.

 

How do you know that the transmission is 'error free'? Unless you're comparing the input and output data on a bit-by-bit level, dvi_demo with a couple of monitors attached probably isn't a great way to reliably test for errors. If you really wanted to test the limits of your Spartan-6, you could connect it up to some expensive HDMI test equipment, or roll something yourself with a much faster FPGA board with HDMI I/O - generate some tricky test patterns, and compare them at both ends.

 

I noticed that XAPP495 only seems to define 24 bits of colour, so I'm not quite sure what will happen if your source signal is sending more than that. HDMI 1.3 only seems to support 30, 36, and 48 bit colour depths. I can't actually figure out what would generate a 32-bit signal (why would you send an alpha channel to your TV?).

 

The XAPP495 code is pretty straightforward and Figure 1 gives you a good clue as to how it works. The magic in the dvi_demo implementation seems to be a BUFGMUX that switches the transmitter PLL's input between the outputs from the two receiver PLLs:

 

BUFGMUX tx0_bufg_pclk (.S(select[0]), .I1(rx1_pllclk1), .I0(rx0_pllclk1), .O(tx0_pclk));

The pixel data is selected in a similar manner:

  assign tx0_red          = (select[0]) ? rx1_red   : rx0_red;

 

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Teacher eteam00
Teacher
9,746 Views
Registered: ‎07-21-2009

A few actual digital video formats

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I don't actually know much about HDMI, but isn't the pixel clock just W*H*Refresh = 1680 * 1050 * 60 = 105.84 MHz?

 

In the digital video age, just the active lines and pixels are described in the video format.  In the DVI/HDMI world, there are still horizontal blanking intervals and vertical blanking intervals.  In the case of HDMI, that's where the audio channels data are stuffed.

 

Examples (do the math!) --

              - active pixels -   frame    - all pixels -    DVI/HDMI                

short name    width      height    rate    width   height   pixel clock

 "720P60"      1280         720     60      1650     750       74.25

 "720P50"      1280         720     50      1980     750       74.25

"1080I60"      1920        1080     30      2200    1125       74.25

"1080I50"      1920        1080     25      2640    1125       74.25

"1080P30"      1920        1080     30      2200    1125       74.25

"1080P25"      1920        1080     25      2640    1125       74.25

"1080P24"      1920        1080     24      2750    1125       74.25

 

In the ancient world of analogue video, video formats were described by total video lines (e.g. "525" and "625")

 

Bear in mind that a part marked -2 might work fine at -3 speeds under good conditions

 

Or even -4 or -5 speeds if die is cool enough.

But then there's the TMDS141 digital video buffer.  Check the specs on this device....

 

HDMI 1.3 only seems to support 30, 36, and 48 bit colour depths.

 

"only" ?

 

Note that I left 1080P60 off the above chart.  The Atlys board (Spartan-6) won't (guarantee) support 1080P60 serial domain bandwidth.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Scholar joelby
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Registered: ‎10-05-2010

Re: A few actual digital video formats

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In the digital video age, just the active lines and pixels are described in the video format.  In the DVI/HDMI world, there are still horizontal blanking intervals and vertical blanking intervals.  In the case of HDMI, that's where the audio channels data are stuffed.


Hmm, how do you know in advance how many extra pixels you need? I suppose you'd need to read the spec or something :)

 


Or even -4 or -5 speeds if die is cool enough.

But then there's the TMS144 dgital video buffer.  Check the specs on this device....


Excellent, the TDMS141 apparently supports up to 225 MHz.

 


HDMI 1.3 only seems to support 30, 36, and 48 bit colour depths.

 

"only" ? 


Sorry, I meant "only" in the "any number as long as it's not 32" sense :)

 

 

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Visitor oszillator
Visitor
9,731 Views
Registered: ‎07-18-2011

Re: Limitations of XAPP945 on the Atlys Board

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Hello,

 

thank you for your answers!

 


Where did you get the 147 MHz figure from?

I connected an ATI graphic card and a 16:10 Acer display to the Atlys board. Then, i use PowerStrip to check settings like the pixel clock. It corresponds to what i found at http://tinyvga.com/vga-timing/1680x1050@60Hz .

 

I call a connection error-free, when i cant detect any pixel errors on the display. I should note that i am working in DVI mode  (XAPP 495 does not support HDMI due to the missing encoder/decoder). DVIs maximum color  depth is 24 bit, so thats what i use (was confused by the 32-bit desktop color depth, sorry). According to the DVI specification, greater color modes require dual link. HDMI just increases the pixel clock to transmit deeper color modes (HDMI 1.4 spec, page 85).


Hmm, how do you know in advance how many extra pixels you need? I suppose you'd need to read the spec or something

imho, it is vice versa, the audio codec is chosen by the blanking interval duration such that it fits. I added my resolution to your table:           
width      height    rate    width   height   pixel clock
1650        1080     60     2256     1087      147,14
       

According to table 2 of  Xapp495 Doc, the throughput directly corresponds to the pixel clock. Hence, a 147.14 MHz clock results in a throughput of 1.47 Gbit/s, thats still about 400 Mbit/s more than speed grade -3 should allow. Even SXGA with a pixel clock of 108 MHz should not work, but it does!

 

Maybe there is a mistake on that table? Or do we miss something else?

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Teacher eteam00
Teacher
9,718 Views
Registered: ‎07-21-2009

UPDATED Re: A few actual digital video formats

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Hmm, how do you know in advance how many extra pixels you need? I suppose you'd need to read the spec or something.

 

If I can do it, you can do it!

 

Excellent, the TDMS141 apparently supports up to 225 MHz

 

You have mis-read the TMDS141 datasheet.  It (guarantees) supports up to 75MHz pixel clock, 750Mbits/sec serial data rate on each channel, and 3 serial data channels per DVI/HDMI interface.

 

UPDATE:  I think I'm mistaken on this last point, and joelby is correct.  Please read further in this thread on this same matter.

 

Sorry, I meant "only" in the "any number as long as it's not 32" sense.

 

Typical use (for LCD monitor displays) is 24 bits, not 32, represented as three [ R | G | B ] channels of 8 bits.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
12,326 Views
Registered: ‎07-21-2009

UPDATED: Understanding DVI/HDMI and Atlys, part 2

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XAPP 495 does not support HDMI due to the missing encoder/decoder

 

This is news to me!  HDMI is primarily a physical transport layer standard, with certain requirements for video format support.  Additional video formats may be supported, but such support is optional.

 

I think your imprecise use of words may mislead to unsupported conclusions.

 

imho, it is vice versa, the audio codec is chosen by the blanking interval duration such that it fits. I added my resolution to your table:           

width      height    rate    width   height   pixel clock
1650        1080     60     2256     1087      147,14

 

The audio codec is chosen by the audio source, not the interface physical transport layer, based on sample rate and bits/sample and data encoding.  Perhaps your definition of 'audio codec' differs from mine.

 

In any case, pixel rates which exceed the datasheet specifications for either Spartan-6 or TI TMDS141 may indeed work (and often do work) -- but they are not guaranteed to work.

 

According to table 2 of  Xapp495 Doc, the throughput directly corresponds to the pixel clock. Hence, a 147.14 MHz clock results in a throughput of 1.47 Gbit/s, thats still about 400 Mbit/s more than speed grade -3 should allow.

 

Correct on all points.

 

Even SXGA with a pixel clock of 108 MHz should not work, but it does!

 

1080Mb/sec (108MHz pixel clock) matches the upper limit datasheet spec for -3 speed grade Spartan-6 devices.

 

Maybe there is a mistake on that table? Or do we miss something else?

 

No mistake in the table whatsoever.  The table is for informational puposes.  I point you to the paragraph following Table 2:

 

For the first time, the most popular 720p and 1080i resolution is achievable in most Spartan-6 devices (except the -1L speed grade).

 

I do not detect any representation that Spartan-6  supports any DVI/HDMI video format which exceeds the Spartan-6 datasheet guarantees.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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Scholar joelby
Scholar
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Registered: ‎10-05-2010

Re: A few actual digital video formats

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Sorry if I'm a bit slow Bob, but can you please explain how you get 82.5 MHz?

 

The data sheet I'm looking at says "Supports 2.25 Gbps Signalling Rate" and specifies Icc and Pd figures at a (presumably 'typical') 165 MHz pixel clock, so I thought it was safe to assume it would go faster than 82.5.

 

 

Teacher eteam00
Teacher
9,700 Views
Registered: ‎07-21-2009

Re: A few actual digital video formats

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Sorry if I'm a bit slow Bob, but can you please explain how you get 82.5 MHz?

 

You are entirely within your rights to challenge me on this.

 

I have always read the TMDS141 datasheet as follows:

 

2.25Gb/sec signaling rate represents the aggregate of 3 data channels in the link.  Each channel is 750Mbits/sec, which corresponds to 75Mpixels/sec.

 

My reading (interpretation) could very well be incorrect.  There are references in the datasheet to 'RXC = 165-MHz clock, RX = 1.65-Gbps HDMI pattern', which I would ordinarily read to mean 1.65Gb/sec signaling rate on each data channel.  This actually seems rather plain and simple, now that you bring it to my attention.

 

Hmmm....  I could be entirely wrong on this.  Thanks for the knock on the head.  Not that it will allow the Spartan-6 to run at similar data rates....

 

Well, thanks for keeping me humble!

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Scholar joelby
Scholar
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Registered: ‎10-05-2010

Re: A few actual digital video formats

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No worries! Any suggestion that I know anything about HDMI beyond getting XAPP495 running is a ruse.

 

I had a look around and found a similar-looking chip, the ADV3003, which says:

 

The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps.

 

The TMDS signals are differential, unidirectional, and high speed (up to 2.25 Gbps). The channels that carry the video data must have a controlled impedance, be terminated at the receiver, and be capable of operating up to at least 2.25 Gbps.

 

This seems to state it a bit clearer that the maximum throughput is 3*2.25 Gbps.. or even 4*2.25 if you wanted to invent your own clock recovery scheme. Perhaps oszillator can put the matter to rest by examining the HDMI signal with a 5 GHz oscilloscope!

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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

Re: A few actual digital video formats

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No worries! Any suggestion that I know anything about HDMI beyond getting XAPP495 running is a ruse.

 

Very humble words, spoken by the Wizard of Atlys!

 

The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× the data-word clock frequency for data rates up to 2.25 Gbps.

 

I surrender!

 

I wonder if oszillator's questions are all settled?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor oszillator
Visitor
3,497 Views
Registered: ‎07-18-2011

Re: A few actual digital video formats

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   I wonder if oszillator's questions are all settled?


Yes, all questions settled, although not perfectly satisfying. I will go with:

"In any case, pixel rates which exceed the datasheet specifications for either Spartan-6 or TI TMDS141 may indeed work (and often do work) -- but they are not guaranteed to work."[]

 

Summary: (assuming speedgrade -2)

The official specifications limit the maximum I/O throughout to 950Mbit/s, hence, the officially supported pixel clock limit is 95 Mhz. More may be possible, but is not guaranteed.

 

Thank you for your help!

 

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