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ramanandn
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Registered: ‎01-28-2010

Low frequency clock doubling in Spartan6

Hi folks..a FPGA newbie here. I need to do a clock doubling in Spartan6 device (clkin is 256kHz). DCM wont work since this is below the min freq for the input. Any ideas?

 

Also, just for kicks when I tried to instatiate the DCM_SP module in my code, I got the compiler error "FALSE is not declared".TRUE, FALSE are used for some strap settings on the primitive. Any libraries that I need to declare to handle TRUE/FALSE (since there's no boolean keyword in verilog)??

 

Thanks

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mcgett
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Registered: ‎01-03-2008

FALSE needs to be quotes "FALSE" for Verilog parameters. 
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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barriet
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Registered: ‎08-13-2007

You can't use the S6 PLL because you are way outside of its range.

 

Even if you only use the DCM's DFS (CLKFXOUT only), you are still outside of the CLKIN_FREQ_FX and CLKOUT_FREQ_FX specs. You may have enough PVT margin that it could work in the lab or for a personal project, but I certainly wouldn't use it on any production designs.

 

Some have the appreciated the ideas in this article:

http://www.pldworld.com/_xilinx/html/tip/sixeasypieces.htm

 

bt

 

 

== edit

For future reference, you may find the instantiation templates in the Library Guide (e.g. spartan6_hdl.pdf) and the ProjNav Language Templates (Verilog -> Device Primitive Instantiation -> Spartan-6 -> Clock Components) useful.

Message Edited by timpe on 01-28-2010 04:28 PM
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woutersj
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Registered: ‎07-27-2009

Yikes! ;-)

 

The article mentions a potential duty cycle issue with the clock doubler circuit. If you want a clean duty cycle, you can probably put 2 of these circuits in series and put a toggle flop at the end to get a nice duty cycle.

 

Can regular synthesis etc. handle this kind of circuit or is it better to just instance and place the logic manually?

 

Cheers,

Johan

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palvarez
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Registered: ‎11-24-2009

Hi,

 

If you do not care much about the skew of your clocks, you could you try to doit with a delay line and an xor gate. If you are using vhdl or verilog you can easily infer a delay line by doing an 'and' of your clock with an IOB tied to a pull up.

 

I hope it helps.

 

pablo

 

 

 

 

 

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